Method and system for fabricating floating guard rings in GaN materials
View Patent ↗A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.
1. A semiconductor structure comprising:
a GaN substrate having a first surface and a second surface opposing the first surface, wherein the GaN substrate is characterized by a first conductivity type and a first dopant concentration;
a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate; and
a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer, wherein the second GaN epitaxial layer comprises:
an active device region;
an edge termination region; and
an implantation region disposed between the active device region and the edge termination region, the implantation region comprising a doped portion of the second GaN epitaxial layer electrically isolating the active device region from the edge termination region.
2. The semiconductor structure of claim 1 further comprising a metallic structure electrically coupled to the first surface of the GaN substrate.
3. The semiconductor structure of claim 1 further comprising a Schottky contact electrically coupled to the active device region.
4. The semiconductor structure of claim 3 wherein the active device region further comprises:
an exposed portion of the first GaN epitaxial layer; and
a Schottky contact electrically coupled to the exposed portion of the first GaN epitaxial layer.
5. The semiconductor structure of claim 3 further comprising:
a metallic field plate coupled to the Schottky contact and extending laterally over at least a portion of the edge termination region; and
a dielectric layer electrically isolating the edge termination region from the metallic field plate.
6. The semiconductor structure of claim 1 wherein the active device region includes at least a portion of a PN diode, the PN diode comprising at least a portion of the first GaN epitaxial layer and at least a portion of the second GaN epitaxial layer.
7. The semiconductor structure of claim 1 wherein the active device region includes one or more elements of a JFET.
8. The semiconductor structure of claim 1 wherein the active device region includes at least a portion of a vertical Schottky diode.
9. The semiconductor structure of claim 1 further comprising a metallic field plate coupled to the edge termination region.
10. The semiconductor structure of claim 1 wherein the edge termination region circumscribes the active device region.
11. The semiconductor structure of claim 1 wherein the edge termination region comprises three or more edge termination elements with a plurality of spacings between each of the edge termination elements, each of the edge termination elements electrically isolated from at least one other edge termination element by at least one additional implantation region.