IP Library Granted Patent US 8,673,730
Granted Patent B2
US 8,673,730 · App. 13/301,255 · Granted Mar 18, 2014

Manufacturing method of charging capacity structure

Inventors: Pei-Chun Hung (Taichung, TW); Li-Hsun Chen (Taichung, TW); Chien-hua Tsai (Taichung, TW); Masahiko Ohuchi (Taichung, TW); Sheng-chang Liang (Taichung, TW)
Assignee: Rexchip Electronics Corporation
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Quick Facts
Patent No.
US 8,673,730
App. No.
13/301,255
Granted
Mar 18, 2014
Kind
B2
Abstract

A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.

Claims (18)

1. A method of manufacturing a charging capacity structure, comprising the steps of:

S 1 : forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence;

S 2 : forming a plurality of etching holes on a surface of the second oxide layer in a matrix to run through the support layer, the first oxide layer and the substrate, the plurality of etching holes being spaced from each other at a selected distance;

S 3 : depositing a pillar layer on a wall surface of each of the plurality of etching holes;

S 4 : removing the second oxide layer to allow a portion of the pillar layer to protrude outside a surface of the support layer to form a plurality of pillar tubes;

S 5 : forming an etching protection layer on the surface of the support layer and on surfaces of the plurality of pillar tubes that is formed at a thickness equal to one half of a spaced distance between the etching holes, the pillar tubes at diagonal locations forming a self-calibration hole;

S 6 : removing the etching protection layer and the support layer in the self calibration hole via anisotropic etching;

S 7 : removing the first oxide layer via wet etching by injecting an etchant into the self-calibration hole to retain the pillar tubes formed from the pillar layer; and

S 8 : fabricating capacitors through the pillar tubes.

2. The method of claim 1 , wherein the first oxide layer and the second oxide layer at the step S 1 are made of a same material selected from the group consisting of silicon dioxide, borophosphosilicate glass and phosphorosilicate glass.

3. The method of claim 1 , wherein the first oxide layer at the step S 1 is formed at a thickness ranged from 500 nm to 3000 nm and the second oxide layer is formed at a thickness ranged from 100 nm to 600 nm.

4. The method of claim 1 , wherein the substrate and the support layer at the step S 1 are respectively made of silicon nitride.

5. The method of claim 1 , wherein the step S 3 further includes the steps of:

S 31 : forming the pillar layer on surfaces of the second oxide layer and the etching holes by deposition; and

S 32 : removing the pillar layer deposited on the surface of the second oxide layer.

6. The method of claim 1 , wherein the pillar layer at the step S 3 is made of titanium nitride.

7. The method of claim 1 , wherein the etching protection layer at the step S 5 is formed via atomic layer deposition.

8. The method of claim 1 , wherein the surfaces of the pillar tubes at the step S 8 are coated by a high dielectric layer, an electrode layer and a polycrystalline layer in sequence to form the capacitors.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2015
From: MICRON MEMORY TAIWAN CO., LTD.,
To: MICRON TECHNOLOGY, INC
Reel/Frame 037222/0690 →
CHANGE OF NAME Recorded Dec 7, 2015
From: REXCHIP ELECTRONICS CO., LTD.
To: MICRON MEMORY TAIWAN CO., LTD.
Reel/Frame 037223/0279 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2011
From: HUNG, PEI-CHUN; CHEN, LI-HSUN; TSAI, CHIEN-HUA; OHUCHI, MASAHIKO; LIANG, SHENG-CHANG
To: REXCHIP ELECTRONICS CORPORATION
Reel/Frame 027268/0595 →
Continuity (1)
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