IP Library Granted Patent US 8,613,861
Granted Patent B2
US 8,613,861 · App. 13/313,566 · Granted Dec 24, 2013

Method of manufacturing vertical transistors

Inventors: Hsiao-chia Chen (Taichung, TW); Sheng-chang Liang (Taichung, TW); Chien-hua Tsai (Taichung, TW); Masahiko Ohuchi (Taichung, TW)
Assignee: Rexchip Electronics Corporation
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Quick Facts
Patent No.
US 8,613,861
App. No.
13/313,566
Granted
Dec 24, 2013
Kind
B2
Abstract

A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.

Claims (17)

1. A. method of manufacturing vertical transistors, comprising the steps of:

S 1 : forming a substrate with two opposing support portions spaced from each other at a selected distance to form a trench which includes a bottom wall and two side walls connecting to the bottom wall, each of the support portions including a top wall remote from the bottom wall of the trench;

S 2 : covering a conductive layer on the bottom wall and the side walls of the trench and the top walls of the support portions via chemical vapor deposition;

S 3 : removing the conductive layer on the bottom wall of the trench and the top walls of the support portions via anisotropic etching through an etch back process;

S 4 : forming an oxidized portion in the trench which includes the conductive layer;

S 5 : etching a portion of the oxidized portion until reaching a selected elevation; and

S 6 : etching the conductive layer until reaching the selected elevation to form in two gates without contacting each other,

wherein the step S 4 includes the steps of:

S 41 : providing protective layer on surfaces of the conductive layer and the bottom wall of the trench;

S 42 : filling an oxidized material in the protective layer to fOrm the oxidized portion;

S 43 : annealing and hardening the oxidized portion; and

S 44 : flattening the oxidized portion via chemical mechanical polishing.

2. The method of claim. 1 further including a step A 1 between the step S 1 and step S 2 by forming an etching stop layer on the bottom wall of the trench and the top walls of the support portions.

3. The method of claim 1 , wherein the conductive layer at the step S 2 is made of metal or material with metal.

4. The method of claim 3 , wherein the conductive layer at the step S 2 is made of tungsten or titanium nitride.

5. The method of claim 1 , wherein the oxidized portion at the step S 42 is made of a spin-on dielectric.

6. The method of claim 1 further including a step S 7 after the step S 6 by etching the conductive layer continuously beyond the selected elevation to prevent the conductive layer from remaining on the side walls of the trench.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2015
From: MICRON MEMORY TAIWAN CO., LTD.,
To: MICRON TECHNOLOGY, INC
Reel/Frame 037222/0690 →
CHANGE OF NAME Recorded Dec 7, 2015
From: REXCHIP ELECTRONICS CO., LTD.
To: MICRON MEMORY TAIWAN CO., LTD.
Reel/Frame 037223/0279 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2011
From: CHEN, HSIAO-CHIA; LIANG, SHENG-CHANG; TSAI, CHIEN-HUA; OHUCHI, MASAHIKO
To: REXCHIP ELECTRONICS CORPORATION
Reel/Frame 027343/0614 →
Continuity (1)
Related Publication 20130146561A1 · Jun 13, 2013