Granted Patent B2

US 8,829,574 · App. 13/334,514 · Granted Sep 9, 2014

Abstract

Claims (23)

1. A semiconductor device comprising:

a III-nitride substrate;

a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa;

a second III-nitride epitaxial layer coupled to a top surface of the mesa;

a III-nitride gate structure contacting a side surface of the mesa; and

a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure, wherein the spacer overlaps the mesa.

2. The semiconductor device of claim 1 wherein:

the III-nitride substrate, the first III-nitride epitaxial layer, and the second III-nitride epitaxial layer are of a first conductivity type; and

the III-nitride gate structure is of a second conductivity type.

3. The semiconductor device of claim 1 further comprising:

a first metal structure coupled to the III-nitride gate structure; and

a second metal structure coupled to the second III-nitride epitaxial layer.

4. The semiconductor device of claim 3 further comprising:

a third metal structure coupled to the first metal structure and the second metal structure; and

a dielectric layer disposed between the third metal structure and at least a portion of the first metal structure and the second metal structure.

5. The semiconductor device of claim 1 wherein:

the semiconductor device comprises a vertical JFET;

the III-nitride substrate comprises a drain of the vertical JFET;

the second III-nitride epitaxial layer comprises a source of the vertical JFET; and

the III-nitride gate structure comprises a gate of the vertical JFET.

6. The vertical JFET of claim 5 wherein:

a drift region of the vertical JFET is formed by the first III-nitride epitaxial layer; and

a channel region of the vertical JFET is formed by the mesa.

Assignments (13)