Integrated circuit with a thin body field effect transistor and capacitor
An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.
1. An integrated circuit comprising:
a transistor including:
a first semiconductor layer;
a gate stack located on the first semiconductor layer, the gate stack comprising a metal layer and a first high-k dielectric layer;
a gate spacer located on sidewalls of the gate stack, the first high-k dielectric layer being located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer;
first and second source/drain regions formed in a second semiconductor layer that is located on and in contact with the first semiconductor layer, the first and second source/drain regions being located on opposite sides of the gate stack;
a first silicide region located on the first source/drain region; and
a second silicide region located on the second source/drain region; and
a capacitor including:
a first terminal comprising a third silicide region located on a portion of the second semiconductor layer that is located on and in contact with the first semiconductor layer;
a second high-k dielectric layer located on the third silicide region; and
a second terminal comprising a metal layer that is located on the second high-k dielectric layer.
2. The integrated circuit of claim 1 , wherein the first and second high-k dielectric layers comprise the same material.
3. The integrated circuit of claim 2 , wherein the metal layer of the gate stack and the metal layer of the second terminal comprise the same material.
4. The integrated circuit of claim 1 ,
wherein the first high-k dielectric layer comprises a first high-k dielectric material, and
the second high-k dielectric layer comprises a second high-k dielectric material, which is different than the first high-k dielectric material.
5. The integrated circuit of claim 4 ,
wherein the metal layer of the gate stack comprises a first metal, and
the metal layer of the second terminal comprises a second metal, which is different than the first metal.
6. The integrated circuit of claim 1 ,
wherein the first high-k dielectric layer and the second high-k dielectric layer comprise a substantially similar high-k dielectric material, and
a thickness of the first high-k dielectric layer is different than a thickness of the second high-k dielectric layer.
7. The integrated circuit of claim 1 , further comprising:
a substrate; and
a buried insulator layer above the substrate, the first semiconductor layer being located on the buried insulator layer.
8. The integrated circuit of claim 1 , wherein the first semiconductor layer has a thickness of less than about 10 nanometers.
9. The integrated circuit of claim 1 , wherein the first and second source/drain regions are one of raised source/drain regions and merged source/drain regions.
10. An information processing system comprising at least one integrated circuit, the integrated circuit comprising:
a transistor including:
a first semiconductor layer;
a gate stack located on the first semiconductor layer, the gate stack comprising a metal layer and a first high-k dielectric layer;
a gate spacer located on the first semiconductor layer and sidewalls of the gate stack, the first high-k dielectric layer being located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer;
first and second source/drain regions formed in a second semiconductor layer that is located on and in contact with the first semiconductor layer, the first and second source/drain regions being located on opposite sides of the gate stack;
a first silicide region located on the first source/drain region; and
a second silicide region located on the second source/drain region; and
a capacitor including:
a first terminal comprising a third silicide region located on a portion of the second semiconductor layer that is located on and in contact with the first semiconductor layer;
a second high-k dielectric layer located on the third silicide region, wherein a width of the second high-k dielectric layer is less than a width of the third silicide region; and
a second terminal comprising a metal layer that is located on the second high-k dielectric layer, wherein second high-k dielectric comprises vertical sidewalls adjacent to the metal layer.
11. The information processing system of claim 10 ,
wherein the first high-k dielectric layer comprises a first high-k dielectric material, and
the second high-k dielectric layer comprises a second high-k dielectric material, which is different than the first high-k dielectric material.
12. The information processing system of claim 10 ,
wherein the first high-k dielectric layer and the second high-k dielectric layer comprise a substantially similar high-k dielectric material, and
a thickness of the first high-k dielectric layer is different than a thickness of the second high-k dielectric layer.