High voltage electrostatic discharge clamp using deep submicron CMOS technology
View Patent ↗An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.
1. An electrostatic discharge (ESD) circuit comprising:
a plurality of metal-oxide-semiconductor (MOS) devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate;
a voltage source inputting a supply voltage to the stack of MOS devices;
a first plurality of resistors equal in number to the number of MOS devices in said stack of MOS devices and configured as a first resistor ladder, wherein each resistor in said first resistor ladder divides said supply voltage to a source and a drain of one MOS device of said plurality of MOS devices in said stack;
a second plurality of resistors equal in number to the number of MOS devices in said stack of MOS devices and configured as a second resistor ladder, wherein each resistor in said second resistor ladder biases said supply voltage to one gate of one MOS device of said plurality of MOS devices in said stack;
an inverter device operatively connected to said second plurality of resistors;
a time lag circuit that turns said inverter device on and off; and
a plurality of capacitors pulling the voltage to each gate of said MOS devices in said stack to said supply voltage upon said inverter device turning off.
2. The ESD circuit of claim 1 , further comprising a diode that keeps a gate voltage of said inverter device higher than a turn-on threshold voltage of said stack of MOS devices.
3. The ESD circuit of claim 1 , wherein said time lag circuit holds a voltage to a gate of said inverter device close to ground in order to turn off said inverter device.
4. The ESD circuit of claim 3 , wherein said stack of MOS devices opens to form a ground return current path upon said inverter device turning off.
5. The ESD circuit of claim 4 , wherein said stack of MOS devices is temporarily opened.
6. The ESD circuit of claim 3 , wherein said inverter device is temporarily turned off.
7. The ESD circuit of claim 1 , wherein a gate-to-source voltage of each of said MOS devices in said stack is less than a turn-on threshold voltage of the MOS devices.
8. The ESD circuit of claim 7 , wherein no leakage current flows through said stack of MOS devices during steady state.
9. The ESD circuit of claim 1 , wherein said stack of MOS devices comprise complementary metal-oxide-semiconductor (CMOS) thick oxide devices.
10. An electrostatic discharge (ESD) circuit comprising a stacked metal-oxide-semiconductor (MOS) device having a biasing structure and time lag circuit that provides current clamping during an ESD event and that is configured to handle DC voltage levels greater than ESD breakdown levels of a MOS device, wherein said stacked MOS device comprises a plurality of MOS devices each comprising a source, a drain, and a gate, and wherein said ESD circuit further comprises:
means for providing a supply voltage to the stacked MOS device;
a first plurality of resistors equal in number to the number of MOS devices in said stacked MOS device and configured as a first resistor ladder, wherein each resistor in said first resistor ladder divides said supply voltage to a source and a drain of one MOS device of said plurality of MOS devices;
a second plurality of resistors equal in number to the number of MOS devices in said stacked MOS device and configured as a second resistor ladder, wherein each resistor in said second resistor ladder biases said supply voltage to each of one gate to one MOS device of said plurality of MOS devices;
an inverter device operatively connected to said second plurality of resistors;
a time lag circuit that turns said inverter device on and off;
a plurality of capacitors pulling the voltage to each gate of said MOS devices in said stack to said supply voltage upon said inverter device turning off; and
a diode that keeps a gate voltage of said inverter device higher than a turn-on threshold voltage of said stack of MOS devices.
11. The ESD circuit of claim 10 , wherein said time lag circuit holds a voltage to a gate of said inverter device close to ground in order to turn off said inverter device, and wherein said stack of MOS devices opens to form a ground return current path upon said inverter device turning off.
12. The ESD circuit of claim 11 , wherein said inverter device is temporarily turned off, and wherein said stack of MOS devices is temporarily opened.
13. The ESD circuit of claim 10 , wherein a gate-to-source voltage of each MOS device in the stacked MOS device is less than a turn-on threshold voltage of the MOS device, and wherein no leakage current flows through said stack of MOS devices during steady state.
14. The ESD circuit of claim 10 , wherein said stacked MOS device comprises complementary metal-oxide-semiconductor (CMOS) thick oxide devices.
15. A method of controlling electrostatic discharge (ESD) in a semiconductor structure, said method comprising:
providing a stack of metal-oxide-semiconductor (MOS) devices, wherein each of the MOS devices comprises a source, a drain, and a gate;
inputting a supply voltage to said stack of MOS devices;
dividing said supply voltage to each source and each drain of said MOS devices in said stack with a plurality of resistors forming a first resistor ladder such that each resistor in said first resistor ladder divides said supply voltage to a source and a drain of one MOS device of said plurality of MOS devices;
biasing said supply voltage to each gate of said MOS devices in said stack with a plurality of resistors forming a second resistor ladder such that each resistor in said second resistor ladder biases said supply voltage to one gate of one MOS device of said plurality of MOS devices;
clamping current through said semiconductor structure during an ESD event occurring in said semiconductor structure; and
pulling voltage to each gate of said MOS devices in said stack to said supply voltage upon said biasing occurring,
wherein no leakage current flows through said stack of MOS devices during steady state.
16. The method of claim 15 , wherein said stack of MOS devices is configured to handle DC voltage levels greater than ESD breakdown levels of said semiconductor structure.