Microprocessor for executing byte compiled java code
View Patent ↗A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities.
1. A microprocessor comprising:
a processor;
a first module including a first set of instructions written in a non-transitory computer-readable medium, the first module configured to execute the first set of instructions in bytecode in the processor;
a second module including a second set of instructions written in a non-transitory computer-readable medium, the second module configured to execute the second set of instructions as microcode in the processor; and
a data path shared by the first and second modules for accessing the processor, the data path including a storage section shared by both modules, the first and second modules configured to access the storage section independently, the first module accessing the storage section as an operand stack and the second module accessing the storage section as a register file.
2. The microprocessor of claim 1 , wherein the first module includes a virtual processor based on an object-oriented programming language.
3. The microprocessor of claim 2 , wherein the second module includes a Reduced Instruction Set Computer (RISC) module.
4. The microprocessor of claim 3 , wherein the second set of instructions are based on the object-oriented programming language, and
wherein the first module is not configured for processing the second set of instructions.
5. The microprocessor of claim 4 , wherein the second set of instructions include at least one of instructions of type float, instructions of type double and instructions of type long.
6. The microprocessor of claim 4 , wherein the second set of instructions include at least one of interrupt instructions and non-interrupt instructions that are not implemented by the first module.
7. The microprocessor of claim 1 , wherein the storage section is structured as the register file, and wherein the register file is configured to be operable as a push-pop stack by the first module, and as a load/store register file by the second module.
8. The microprocessor of claim 7 , wherein the register file includes a first number of elements, and wherein the first module is configured for accessing the register file as the push-pop stack having a second number of elements that is around half the first number of elements.
9. The microprocessor of claim 8 , wherein a remaining number of elements of the register file other than the second number of elements are configured for implementing special registers that are used for operation of the first and second modules.
10. The microprocessor of claim 9 , wherein the special registers include at least one of a program counter, a program counter base register that is configured for storing an address of an instruction routine that invokes the first module, a constant pool base address register, a local variable base address register that is configured for storing an address of a local variable used by the first module, a status register, a stack pointer for the first module that is configured for storing a location of a top of the push-pop stack, a stack pointer for the second module that is configured for storing a memory address used by the second module for temporary variable storage, scratch registers and stack control registers.
11. The microprocessor of claim 8 , wherein the second module is configured for accessing the first number of elements included in the register file.
12. A method comprising:
initializing a microprocessor that includes a processor, a first module that is configured to execute a first set of instructions in bytecode in the processor, and a second module that is configured to execute a second set of instructions as microcode in the processor;
executing an initialization code by the processor in a second mode in which the second module executes the second set of instructions as microcode in the processor;
switching operation of the microprocessor to a first mode in which the first module executes the first set of instructions in bytecode in the processor;
determining whether an interrupt has occurred;
based on determining that an interrupt has occurred, executing an instruction by the processor in the first mode for switching operation of the microprocessor to the second mode;
responsive to executing the instruction, changing operation of the microprocessor to the second mode;
processing the interrupt by the processor in the second mode using the second module executing the second set of instructions as microcode in the processor; and
changing operation of the microprocessor to the first mode when processing the interrupt event is completed, wherein the first mode resumes execution of the first set of instructions in bytecode in the processor.
13. The method of claim 12 , wherein determining whether an interrupt has occurred further comprises:
determining whether an instruction that is not implemented by the first module is to be executed; and
based on determining that an instruction that is not implemented by the first module is to be executed, executing the instruction by the processor in the second mode using the second module.
14. The method of claim 12 , wherein the first and second modules use a shared data path to access a shared storage section included in the shared data path, the first and second modules accessing the shared storage section for storing memory addresses and variables that facilitate changing operation of the microprocessor between the first and second modes.
15. The method of claim 14 , wherein the first module accesses the shared storage section as a push-pop stack, and the second module accesses the shared storage section as a register file.
16. The method of claim 15 , wherein determining whether an interrupt has occurred further comprises:
determining, by the processor, whether implementation specific conditions are true;
based on determining that implementation specific conditions are true, jumping to a predefined address and changing operation of the microprocessor to the second mode;
storing a return address in the register file;
processing the interrupt using the second module executing the second set of instructions as microcode in the processor; and
changing to the first mode of operation of the microprocessor by executing an interrupt return instruction in which the return address is read from the register file.
17. The method of claim 15 , wherein determining whether an interrupt has occurred further comprises:
determining whether an instruction that is not implemented by the first module is to be executed;
based on determining that an instruction that is not implemented by the first module is to be executed, storing, by the first module, a return address on top of the push-pop stack;
fetching, by the processor, a jump address from a predefined location in memory and changing operation of the microprocessor to the second mode;
executing an instruction associated with the jump address by the processor in the second mode using the second module;
retrieving, by the second module, the return address from the push-pop stack when executing the instruction is completed;
storing, by the second module, the return address in a program counter register included in the shared storage section; and
changing operation of the microprocessor to the first mode such that the first mode is enabled to resume operation using the return address stored in the program counter.
18. The method of claim 15 , comprising:
executing an instruction by the processor in the second mode using the second module executing the second set of instructions as microcode in the processor; and
setting, by the second module, status bits included in the register file for using a value from a top of the push-pop stack as an operand when executing the instruction, the status bits indicating at least one of a source and destination operand that are associated with the first module.
19. The method of claim 14 , wherein the first or the second module executes the first or second set of instructions respectively in the processor based on a value of a control bit included in the shared storage section, the control bit serving as a control input for the shared data path.