Serial bit processor
A serial bit processor is disclosed that configures a timer/counter module to determine a number of data bits to be decoded from a serial bit stream. In some implementations, a serial peripheral is coupled to a timer/counter module. The serial peripheral sends a restart command to reload an internal count register of the timer/counter module with a pre-defined value. The serial peripheral then sends count commands that cause the timer/counter to decrement (or increment) by one each time a count command is received. When the count reaches zero, a compare match command is generated and sent to the serial peripheral where it is used to resume or complete the decoding of data bits from the serial bit stream. In some implementations, a serial peripheral is included in a microcontroller that has an event system. The event system is used to communicate commands between peripherals.
1. A serial bit processor comprising:
a serial peripheral configured to receive a serial bit stream including data frames having data fields containing data bits; and
a timer/counter module coupled to the serial peripheral and configured to generate an outbound command for use by the serial peripheral to decode the data bits from the data fields, where the outbound command is based on inbound commands provided by the serial peripheral, where the inbound commands control decrementing or incrementing of a timer or counter in the timer/counter module, and a first command of the inbound commands starts or restarts the timer or counter and a second command of the inbound commands causes the timer or counter to decrement or increment.
2. The serial bit processor of claim 1 , further comprising:
an event system coupled to the serial peripheral and the timer/counter module and configured to communicate the input commands and the output command between the serial peripheral and the timer/counter module.
3. The serial bit processor of claim 1 , where the outbound command is used to control operation of the timer/counter module.
4. The serial bit processor of claim 1 , where the timer/counter module can be configured with a count value indicative of a length of the data fields.
5. The serial bit processor of claim 1 , where the serial peripheral further comprises:
a finite state machine (FSM) configured to generate the inbound commands provided to the timer/counter module.
6. The serial bit processor of claim 5 , where the FSM is configured to receive the outbound command from the timer/counter module and use the outbound command to decode data bits from the serial bit stream.
7. The serial bit processor of claim 6 , where the FSM includes a state that generates the first inbound command for starting or restarting the timer or counter in the timer/counter module, and a state that generates the second inbound command for causing the timer or counter to decrement or increment.
8. A method performed by a serial bit processor including a serial peripheral coupled to a timer/counter module, the method comprising:
receiving a serial bit stream including data frames having data fields containing data bits; and
generating an outbound command for use by a serial peripheral to decode the data bits from the data fields, where the command is based on inbound commands provided by a serial peripheral, where the inbound commands control the decrementing or incrementing of a timer or counter in the timer/counter module, and a first command of the inbound commands starts or restarts the timer or counter and a second command of the inbound commands causes the timer or counter to decrement or increment.
9. The serial bit processor of claim 8 , further comprising:
an event system coupled to the serial peripheral and the timer/counter module and configured to communicate the input commands and the output command between the serial peripheral and the timer/counter module.
10. The serial bit processor of claim 8 where the outbound command is used to control the operation of the timer/counter module.
11. The serial bit processor of claim 8 , where the timer/counter module can be configured with a count value indicative of a length of the data fields.
12. The serial bit processor of claim 8 , where the serial peripheral further comprises:
a finite state machine (FSM) configured to generate the inbound commands provided to the timer/counter module.
13. The serial bit processor of claim 12 , where the FSM is configured to receive the outbound command from the timer/counter module and use the outbound command to decode data bits from the serial bit stream.
14. The serial bit processor of claim 13 , where the FSM includes a state that generates the first inbound command for starting or restarting the timer or counter in the timer/counter module, and a state that generates the second inbound command for causing the timer or counter to decrement or increment.