Intelligent scheduling of background operations in memory
A memory system or flash card may include an algorithm for identifying a pattern in a sustained or continuous write operation. In one example, a video recording device may be a host that continuously writes data to a memory card in an identifiable pattern. The pattern identification algorithm may be stored in the firmware of the memory card and used to schedule background operations during the predicted idle times in which the host is not writing data to the memory card.
1. A flash memory device comprising:
a non-volatile storage having an array of memory blocks storing data; and
a controller in communication with the non-volatile storage, the controller is configured for:
receiving data chunks from a host to be stored in the non-volatile storage;
identifying, with firmware on the flash memory device, a pattern based on the received data chunks, wherein the pattern comprises data chunks and idle time between successive data chunks; and
scheduling background operations during the idle time.
2. The device of claim 1 wherein the identifying by the controller further comprises:
comparing successive data chunks;
repeating the comparison of successive chunks when the comparison of the successive data chunks indicate a pattern, wherein the pattern identifies the idle time between the successive chunks; and
identifying the pattern after a threshold for the number of data chunks compared is reached.
3. The device of claim 2 wherein the threshold for the number of data chunks to compare is five.
4. The device of claim 2 wherein the comparison of the successive data chunks comprises a comparison of a time for writing each of the data chunks and a comparison of a size of each of the data chunks.
5. The device of claim 4 wherein the pattern is identified when the threshold of the number of chunks compared is reached and when the comparison for time and data size for each of those successive data chunks is within an error limit.
6. The device of claim 2 wherein the identifying by the controller further comprises comparing successive amounts of the idle time, wherein the pattern is indicated when the successive amounts of the idle time are similar within an error limit.
7. The device of claim 1 wherein the identifying by the controller further comprises generating a pattern identification algorithm.
8. The device of claim 7 wherein the pattern identification algorithm is used by a back end of the flash memory device for the scheduling of the background operations.
9. The device of claim 8 wherein the identifying is with a front end of the flash memory device and the scheduling is with a back end of the flash memory device.
10. The device of claim 9 wherein the front end comprises a host interface module and the back end comprises a flash interface module.
11. A memory system comprising:
a non-volatile storage for storing data;
a host interface module for receiving the data to be stored on the non-volatile storage;
a back end interface module for communicating with the non-volatile storage; and
a controller in communication with the host interface module and the back end interface module, wherein the controller is configured for:
utilizing a pattern identification algorithm with the host interface module for identifying a pattern of the received data; and
scheduling background operations with the back end interface module during idle time, further wherein the idle time is predicted based on the pattern identification algorithm.
12. The memory system of claim 11 wherein the non-volatile storage comprises a flash memory.
13. The memory system of claim 12 wherein the back end interface module comprises a flash interface module.
14. The memory system of claim 11 wherein the received data comprises data chunks.
15. The memory system of claim 14 wherein idle time occurs between the data chunks.
16. The memory system of claim 15 wherein the pattern identification algorithm comprises an identification of a timing for each of the data chunks and a timing for when the idle time occurs.
17. The memory system of claim 16 wherein the pattern identification algorithm is generated when the controller is configured for:
comparing successive data chunks;
repeating the comparison of successive data chunks when the comparison of the successive data chunks indicate a pattern; and
recognizing the pattern after a threshold for the number of data chunks compared is reached.
18. The memory system of claim 17 wherein the pattern is recognized when the threshold of the number of data chunks compared is reached and when the comparison for the timing for each of those successive data chunks and successive idle times is within an error limit.
19. The memory system of claim 16 wherein the timing for each of the data chunks comprises a chunk of time in which the data chunk is written and the timing for each of the idle time comprises an amount of time in which there is no writing with the back end interface module.
20. A method for scheduling background operations in a flash memory device comprising:
in a non-volatile storage device having a controller and blocks of memory, the controller:
monitors data chunks received during a sustained write operation and idle time that occurs during a delay between successive data chunks;
compares successive data chunks to determine whether a time and data amount for each of the successive data chunks is equivalent;
repeats the comparison of successive data chunks as long as the successive data chunks are equivalent and until a threshold number of data chunks have been compared; and
recognizes a pattern when the threshold number of data chunks have been compared and each of those successive data chunks are equivalent; and
schedules background operations during the idle time, wherein the pattern comprises recognizing a timing for data chunks and recognizing the idle times during which there is no data chunks to be written.