Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same

1. A memory cell comprising:

a steering element;

a reversible resistance-switching element comprising tantalum coupled to the steering element and formed using a selective deposition process; and

a silicide-forming metal layer disposed between the steering element and the reversible resistance-switching element.

2. The memory cell of claim 1 , wherein the steering element comprises a diode.

3. The memory cell of claim 2 , wherein the diode comprises a vertical polycrystalline diode.

4. The memory cell of claim 3 , wherein the vertical polycrystalline diode includes polycrystalline material that is in a low-resistivity state.

5. The memory cell of claim 2 , wherein the diode comprises a p-n diode or a p-i-n diode.

6. The memory cell of claim 1 , wherein the reversible resistance-switching element comprises a tantalum oxide.

7. The memory cell of claim 1 , wherein the reversible resistance-switching element comprises a tantalum-containing layer that is formed by oxidizing or annealing the tantalum-containing layer.

8. The memory cell of claim 7 , wherein the tantalum-containing layer is selectively deposited using an electroless deposition or electroplating process.

9. The memory cell of claim 1 , wherein the steering element and reversible resistance-switching element are coupled in series.

10. A plurality of nonvolatile memory cells comprising:

a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction;

a plurality of diodes;

a plurality of reversible resistance-switching elements each comprising tantalum; and

a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction different from the first direction;

wherein, in each memory cell, one of the diodes and one of the reversible resistance-switching elements are arranged in series between one of the first conductors and one of the second conductors, with a silicide-forming metal disposed between the diode and the reversible resistance-switching element; and

wherein each reversible resistance-switching element is formed using a selective deposition process.

11. The plurality of memory cells of claim 10 , wherein each diode is a vertical polycrystalline diode.

12. The plurality of memory cells of claim 11 , further comprising a silicide, silicide-germanide or germanide region in contact with polycrystalline material of each vertical polycrystalline diode so that the polycrystalline material is in a low-resistivity state.

13. The plurality of memory cells of claim 10 , wherein each reversible resistance-switching element comprises a tantalum oxide.

14. The plurality of memory cells of claim 10 , wherein the selective deposition process comprises an electroless deposition or electroplating process.

15. A monolithic three dimensional memory array comprising:

a first memory level formed above a substrate, the first memory level comprising:

a plurality of memory cells, wherein each memory cell of the first memory level comprises:

a steering element;

a reversible resistance-switching element comprising tantalum coupled to the steering element and formed using a selective deposition process; and

a silicide-forming metal layer disposed between the steering element and the reversible resistance-switching element; and

a second memory level monolithically formed above the first memory level.

16. The monolithic three dimensional memory array of claim 15 , wherein each steering element comprises a vertical polycrystalline diode.

17. The monolithic three dimensional memory array of claim 16 , wherein each vertical polycrystalline diode comprises a vertical polysilicon diode.

18. The monolithic three dimensional memory array of claim 15 , wherein each reversible resistance-switching element comprises a tantalum oxide.

19. The monolithic three dimensional memory array of claim 15 , wherein a respective steering element and reversible resistance-switching element of each memory cell are coupled in series.

20. The monolithic three dimensional memory array of claim 15 , wherein 14 the selective deposition process comprises an electroless deposition or electroplating process.