Granted Patent B2

US 9,658,682 · App. 13/603,155 · Granted May 23, 2017

Inventors: Patrice Menard (Saint-Mars-du-Desert, FR); Olivier Husson (Nantes, FR); Mickael Le Dily (Carquefou, FR); Thierry Gourbilleau (Le Loroux-Bottereau, FR); Marc Laurent (Nantes, FR); Stefan Schabel (Syrgenstein, DE); Ronan Barzic (Tiller, NO)

Assignee: Atmel Corporation

G06F1/3296G06F1/3243G11C5/147G11C16/30Y02B60/1239Y02B60/1285Y02B60/32

Abstract

Claims (35)

1. A method comprising:

entering a power saving mode;

in response to entering the power saving mode, enabling a lower power reference voltage circuit in a secondary regulator of a regulator circuitry;

after enabling the lower power reference voltage circuit, waiting for a period of time for the lower power reference voltage circuit to provide a lower power reference voltage with a first level of accuracy with respect to a target reference voltage;

when the lower power reference voltage circuit provides the lower power reference voltage, providing, by the lower power reference voltage circuit, the lower power reference voltage to one or more first modules of the microcontroller system;

during a power saving mode of a microcontroller system, disabling a main reference voltage circuit being coupled to a main regulator of the regulator circuitry and comprising a regulation loop, and disabling a secondary reference voltage circuit in a module of the microcontroller system, the main reference voltage circuit being operable to provide a main reference voltage with a second level of accuracy with respect to the target reference voltage, the second level of accuracy being higher than the first level of accuracy;

on exiting the power saving mode, enabling the main reference voltage circuit and the secondary reference voltage circuit in the module of the microcontroller system, the module being external to the regulator circuitry and the main reference voltage circuit, the secondary reference voltage circuit being different from the lower power reference voltage circuit in the secondary regulator and having a faster startup time than the main reference voltage circuit by virtue of the secondary reference voltage circuit lacking the regulation loop of the main reference voltage circuit, the secondary reference voltage circuit being operable to provide a secondary reference voltage;

after enabling the secondary reference voltage circuit, waiting for a period of time for the secondary reference voltage circuit to provide the secondary reference voltage;

selecting the secondary reference voltage circuit so that the secondary reference voltage circuit is providing the secondary reference voltage to the module of the microcontroller system while the main reference voltage circuit is starting up; and

when the main reference voltage circuit provides the main reference voltage, selecting the main reference voltage circuit so that the main reference voltage circuit is providing the main reference voltage to the module and the secondary reference voltage circuit is stopped to provide the secondary reference voltage to the module, and disabling the lower power reference voltage circuit.

2. The method of claim 1 , further comprising:

when the secondary reference voltage circuit provides the secondary reference voltage, enabling the module that is disabled during the power saving mode.

3. The method of claim 1 , wherein the module is a flash memory module, and wherein the secondary reference voltage circuit is within the flash memory module.

4. The method of claim 3 , further comprising performing memory accesses to the flash memory module during a time period between enabling the main reference voltage circuit and selecting the main reference voltage circuit.

5. The method of claim 1 , wherein the main reference voltage circuit draws no power when disabled during the power saving mode.

6. A microcontroller system comprising:

a power state logic controller;

a regulator circuitry comprising a main regulator and a secondary regulator, the secondary regulator including a lower power reference voltage circuit operable to provide a lower power reference voltage with a first level of accuracy with respect to a target reference voltage;

a main reference voltage circuit being coupled to the main regulator and comprising a regulation loop, the main reference voltage circuit being operable to provide a main reference voltage with a second level of accuracy with respect to the target reference voltage, the second level of accuracy being higher than the first level of accuracy;

a module comprising a secondary reference voltage circuit having a faster startup time than the main reference voltage circuit by virtue of the secondary reference voltage circuit lacking the regulation loop of the main reference voltage circuit, the module being external to the regulator circuitry and the main reference voltage circuit, the secondary reference voltage circuit being different from the lower power reference voltage circuit, the secondary reference voltage being operable to provide a secondary reference voltage; and

a selection circuit coupled to the power state logic controller, the regulator circuitry, the main reference voltage circuit, the secondary reference voltage circuit, and the module,

wherein the power state logic controller is configured to:

enter a power saving mode of the microcontroller system;

enable the lower power reference voltage circuit;

wait for a period of time for the lower power reference voltage circuit to provide the lower power reference voltage;

configure the selection circuit to select the lower power reference voltage circuit to provide the lower reference voltage to one or more first modules of the microcontroller system; and

disable the main reference voltage circuit and the secondary reference voltage circuit in the module during the power saving mode of the microcontroller system,

wherein the power state logic controller is configured to:

enable the main reference voltage circuit and the secondary reference voltage circuit on exiting the power saving mode,

wait for a period of time for the secondary reference voltage circuit to provide the secondary reference voltage after enabling the secondary reference voltage circuit,

configure the selection circuit to select the secondary reference voltage circuit while the main reference voltage circuit is starting up, and

configure the selection circuit to select the main reference voltage circuit when the main reference voltage circuit provides the main reference voltage.

7. The system of claim 6 , wherein the power state logic controller is configured to, after the secondary reference voltage circuit provides the secondary reference voltage, enable the module.

8. The system of claim 6 , wherein the module is a flash memory module, and wherein the secondary reference voltage circuit is within the flash memory module.

9. The system of claim 8 , wherein the flash memory module is configured to perform memory accesses during a time period between enabling the main reference voltage circuit and configuring the selection circuit to select the main reference voltage circuit.

Assignments (21)

Continuity (2)