Microcontroller input/output connector state retention in low-power modes
A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.
1. A microcontroller operable in a low-power mode, the microcontroller comprising:
one or more I/O connectors;
an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors, wherein the I/O controller is powered off or deactivated during the low-power mode; and
I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller, wherein the I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.
2. The microcontroller of claim 1 wherein the I/O connector state retention logic includes a plurality of latches each of which is operable to be enabled to latch a respective one of the control signals from the I/O controller.
3. The microcontroller of claim 2 further including a power state manager that provides a signal to cause the latches to latch the respective control signals when the microprocessor enters the low-power mode.
4. The microcontroller of claim 3 wherein, when the microprocessor exits the low-power mode, the power state manager releases the signal that caused the latches to latch the respective control signals.
5. The microcontroller of claim 1 wherein the control signals from the I/O controller include one or more of: a first signal to drive a logical one or zero onto the particular I/O connector, a second signal to select whether the particular I/O connector is used as an input or an output, and a third signal that selects a drive strength setting.
6. The microcontroller of claim 1 wherein the control signals from the I/O controller collectively include: a first signal to drive a logical one or zero onto the particular I/O connector, a second signal to select whether the particular I/O connector is used as an input or an output, and a third signal that selects a drive strength setting.
7. The microcontroller of claim 1 wherein the I/O connectors are in the form of I/O pads or I/O pins.
8. A microcontroller operable in a low-power mode, the microcontroller comprising:
one or more I/O connectors;
an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors, wherein the I/O controller is powered off or deactivated during the low-power mode;
I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller, wherein the I/O connector state control logic includes I/O connector state retention logic that retains respective states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode, thereby executing an I/O connector state retention function;
a power state manager; and
a user interface that, depending on a value stored in a register of the user interface, allows either automated I/O connector state retention by the power state manager or user-controlled I/O connector state retention.
9. The microcontroller of claim 8 wherein, if a first value is stored in the register, the user interface allows the power state manager to initiate execution of the I/O connector state retention function automatically when the microprocessor enters the low-power mode, and allows release of the I/O connector state retention function automatically when the microprocessor exits the low-power mode.
10. The microcontroller of claim 9 wherein the user interface allows execution of the I/O connector state retention function prior to the microprocessor entering the low-power mode at a time specified by user input, if a second value is stored in the register.
11. The microcontroller of claim 10 wherein the user interface allows release of the I/O connector state retention function after the microprocessor exits the low-power mode at a time specified by user input, if the second value is stored in the register.
12. The microcontroller of claim 8 wherein the I/O connector state retention logic includes a plurality of latches each of which is operable to be enabled to latch a respective one of the control signals from the I/O controller.
13. The microcontroller of claim 12 wherein the power state manager provides a signal to cause the latches to latch the respective control signals when the microprocessor enters the low-power mode.
14. The microcontroller of claim 13 wherein, when the microprocessor exits the low-power mode, the power state manager releases the signal that caused the latches to latch the respective control signals.
15. The microcontroller of claim 8 wherein the control signals from the I/O controller include: a first signal to drive a logical one or zero onto the particular I/O connector, a second signal to select whether the particular I/O connector is used as an input or an output, and a third signal that selects a drive strength setting.
16. A method of retaining the state of an I/O connector of a microcontroller, the method comprising:
generating, from an I/O controller in the microcontroller, one or more control signals for controlling a state of the I/O connector;
causing the microcontroller to enter a low-power mode of operation, in which the I/O controller is powered off or deactivated;
storing information indicative of the respective states of the one or more control signals prior to the I/O controller becoming powered off or deactivated; and
maintaining the I/O connector in a corresponding state in accordance with the stored information while the microcontroller is in the low-power mode.
17. The method of claim 16 wherein storing information indicative of the respective states of the one or more control signals includes latching each of the respective control signals when the microcontroller enters the low-power mode.
18. The method of claim 17 including returning control of the one or more control signals to the I/O controller automatically when the microcontroller exits the low-power mode.
19. The method of claim 17 further including releasing latching of the one or more control signals automatically when the microcontroller exits the low-power mode.
20. The method of claim 16 wherein the one or more control signals include one or more of: a first signal to drive a logical one or zero onto the particular I/O connector, a second signal to select whether the particular I/O connector is used as an input or an output, and a third signal that selects a drive strength setting.