Granted Patent B2

US 9,075,588 · App. 13/608,705 · Granted Jul 7, 2015

Inventors: Lutz Dathe (Dresden, DE); Henry Drescher (Radebeul, DE); Thomas Hanusch (Coswig, DE)

Assignee: Atmel Corporation

G06F1/26G06F1/3287G06F1/266

Abstract

Claims (53)

1. A circuit comprising:

a voltage regulator configured to:

generate a supply voltage in response to an enable signal, the supply voltage connected to each switch in a chain of switches; and

generate a supply voltage status signal, the supply voltage status signal indicating a status of the supply voltage;

a controller configured to transmit the enable signal to the voltage regulator in response to a request signal; and

an arithmetic logic unit configured to transmit the request signal;

the chain of switches comprising:

a first switch configured to switch the supply voltage to a first subcircuit of a plurality of subcircuits based on the supply voltage status signal; and

one or more second switches configured to switch the supply voltage to one or more respective subcircuits of the plurality of subcircuits.

2. The circuit of claim 1 , wherein:

each switch in the chain of switches is configured to generate a switch state status signal indicating a switch state of the respective switch.

3. The circuit of claim 2 , wherein:

each of the one or more second switches is configured to connect the supply voltage to its respective subcircuit based on the switch state status signal generated by a previous switch in the chain of switches.

4. The circuit of claim 1 , wherein:

the controller is configured to transmit a disconnect signal to at least one switch in the chain of switches; and

the at least one switch in the chain of switches is configured to disconnect the supply voltage from its respective subcircuit in response to the disconnect signal.

5. The circuit of claim 1 , wherein the controller is configured to transmit a clock enable signal to at least one of the plurality of subcircuits, the clock enable signal causing the at least one of the plurality of subcircuits to enable a respective clock.

6. The circuit of claim 2 , wherein the controller is configured to transmit a clock enable signal to at least one of the plurality of subcircuits based on the switch state status signal generated by a last switch in the chain of switches, the clock enable signal causing the at least one of the plurality of subcircuits to enable a respective clock.

7. The circuit of claim 2 , wherein:

the controller is configured to transmit a confirmation signal to the arithmetic logic unit based on the switch state status signal generated by a last switch in the chain of switches; and

the arithmetic logic unit accesses at least one of the plurality of subcircuits based on the confirmation signal.

8. The circuit of claim 1 , wherein the controller is configured to place the circuit in a sleep mode with reduced current consumption.

9. A method comprising:

generating, by a voltage regulator, a supply voltage, the supply voltage connected to each switch in a chain of switches, the chain of switches comprising a first switch and one or more second switches;

generating, by the voltage regulator, a supply voltage status signal indicating a status of the supply voltage;

switching, by the first switch, the supply voltage to a respective one of a plurality of subcircuits based on the supply voltage status signal;

switching, by each of the second switches, the supply voltage to a respective one of the plurality of subcircuits;

transmitting, by a controller, an enable signal;

receiving, by the voltage regulator, the enable signal, wherein generating the supply voltage occurs in response to receiving the enable signal; and

receiving, by the controller, a request signal from an arithmetic logic unit, wherein transmitting the enable signal is in response to receiving the request signal.

10. The method of claim 9 , further comprising, generating, by each switch in the chain of switches, a switch state status signal indicating a switch state of the respective switch.

11. The method of claim 10 , wherein switching, by each of the second switches, the supply voltage to the respective one of the plurality of subcircuits is based on the switch state status signal generated by a previous switch in the chain of switches.

12. The method of claim 9 , further comprising:

transmitting, by the controller, a disconnect signal to one or more switches in the chain of switches; and

disconnecting, by the one or more switches in the chain of switches, the supply voltage from the respective subcircuits in response to the disconnect signal.

13. The method of claim 9 , further comprising:

transmitting, by the controller, a clock enable signal to one or more subcircuits of the plurality of subcircuits; and

enabling, by the one or more subcircuits, a respective clock in response to the clock enable signal.

14. The method of claim 10 , further comprising:

transmitting, by the controller, a clock enable signal to one or more subcircuits of the plurality of subcircuits based on the switch state status signal generated by a last switch in the chain of switches; and

enabling, by the one or more subcircuits, a respective clock in response to the clock enable signal.

15. The method of claim 10 , further comprising:

transmitting, by the controller, a confirmation signal to the arithmetic logic unit based on the switch state status signal generated by a last switch in the chain of switches; and

accessing, by the arithmetic logic unit, at least one of the plurality of subcircuits based on the confirmation signal.

16. The method of claim 9 , further comprising:

placing, by the controller, at least one of the voltage regulator and the chain of switches in a sleep mode with reduced current consumption.

17. A system comprising:

means for generating a supply voltage in response to an enable signal;

means for generating a supply voltage status signal, the supply voltage status signal indicating a status of the supply voltage;

means for switching the supply voltage to a first subcircuit of a plurality of subcircuits based on the supply voltage status signal;

means for switching the supply voltage to a respective subcircuit of the plurality of subcircuits;

means for transmitting the enable signal to the means for generating the supply voltage; and

means for receiving a request signal from an arithmetic logic unit and transmitting the enable signal in response to receiving the request signal.

Assignments (18)

Priority Claims (1)

Continuity (3)