IP Library Granted Patent US 9,710,352
Granted Patent B2
US 9,710,352 · App. 13/630,026 · Granted Jul 18, 2017

Microcontroller with integrated monitoring capabilities for network applications

Inventors: Guillaume Pean (Aix en Provence, FR); Pierre Samat (La Ciotat, FR); Sebastien Younes (Pourrieres, FR)
Assignee: Atmel Corporation
G06F11/349H04L63/1425G06F11/348
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Quick Facts
Patent No.
US 9,710,352
App. No.
13/630,026
Granted
Jul 18, 2017
Kind
B2
Abstract

A microcontroller has integrated monitoring capabilities for network applications. The disclosed techniques can take advantage, for example, of an unused, duplicate network controller that is present in some microcontrollers by providing selection circuitry and configuration capabilities that allow the unused, duplicate network controller to be used for the purpose of monitoring frames that are transferred between network media and another network controller residing on the microcontroller. The monitored frames can then be used, for example, for debugging or other purposes, such as statistical analyzes or security enhancements.

Claims (38)

1. A monolithic microcontroller system comprising:

a microprocessor executing instructions stored in one or more on-chip memory devices;

a first set of one or more input/output (I/O) terminals and a different second set of one or more I/O terminals;

a first network controller, wherein the microprocessor is configured to transfer and receive information over the first set of one or more I/O terminals using the first network controller;

a second network controller, wherein the second network controller is different than the first network controller, and wherein the microprocessor is configured to transfer and receive information over the second set of one or more I/O terminals using a first mode of the second network controller and to monitor information transferred or received by the first network controller over the first set of one or more I/O terminals using a second mode of the second network controller, wherein monitoring information transferred or received by the first network controller comprises storing an indication of one more missed frames of information; and

selection circuitry operable to couple the second network controller either to the first set of one or more I/O terminals or to the second set of one or more I/O terminals,

wherein, when the second network controller is configured in the first mode, the selection circuitry establishes a first path from the second network controller to the second set of one or more I/O terminals and when the second network controller is configured in the second mode, the selection circuitry provides a second path from the second network controller to the first set of one or more I/O terminals, the second path bypassing the first network controller.

2. The monolithic microcontroller system of claim 1 wherein the second network controller includes an internal buffer for storing frames received by the second network controller when it is in the second mode, wherein the frames are transferred or received over the first set of one or more I/O terminals.

3. The monolithic microcontroller system of claim 2 further including a DMA controller, wherein the DMA controller is operable to transfer contents of the buffer to memory.

4. The monolithic microcontroller system of claim 1 wherein the selection circuitry includes a multiplexor.

5. The monolithic microcontroller system of claim 1

wherein the selection circuitry is operable to couple the second network controller either to the first set of one or more I/O terminals or to the second set of one or more I/O terminals in response to an instruction from the microprocessor.

6. The monolithic microcontroller system of claim 1 further including a register, wherein the selection circuitry is operable to couple the second network controller either to the first set of one or more I/O terminals or to the second set of one or more I/O terminals in response to activation or deactivation of the register.

7. A microcontroller system comprising:

network media; and

a monolithic microcontroller comprising:

a microprocessor executing instructions stored in one or more on-chip memory devices;

a first set of one or more input/output (I/O) terminals coupled to the network media and a different second set of one or more I/O terminals coupled to the network media;

a first network controller, wherein the microprocessor is configured to transfer and receive frames over the first set of one or more I/O terminals using the first network controller;

a second network controller, wherein the second network controller is different than the first network controller, and wherein the microprocessor is configured to transfer and receive frames over the second set of one or more I/O terminals using a first mode of the second network controller and monitor frames passing over the first set of one or more I/O terminals between the first network controller and the network media using a second mode of the second network controller, wherein monitoring information transferred or received by the first network controller over the first set of one or more I/O terminals comprises storing an indication of one more missed frames of information; and

selection circuitry operable to couple the second network controller either to the first set of one or more I/O terminals or to the second set of one or more I/O terminals,

wherein, when the second network controller is configured in the first mode, the selection circuitry establishes a first path from the second network controller to the second set of one or more I/O terminals and when the second network controller is configured in the second mode, the selection circuitry establishes a second path from the second network controller to the first set of one or more I/O terminals, the second path not including the first network controller.

8. The microcontroller system of claim 7

wherein the monolithic microcontroller is operable to couple the second network controller either to the first set of one or more I/O terminals or to the second set of one or more I/O terminals in response to an instruction from the microprocessor.

9. The microcontroller system of claim 7 wherein the monolithic microcontroller further includes selection circuitry to couple the second network controller either to the first set of one or more I/O terminals or to the second set of one or more I/O terminals based on whether or not a specified register is activated.

10. The microcontroller system of claim 7 further including a multiplexor wherein, when the second network controller is configured in the first mode, the multiplexor provides a path between the second network controller and the second set of one or more I/O terminals and when the second network controller is configured in the second mode, the multiplexor provides a path between the second network controller and the first set of one or more I/O terminals.

11. The microcontroller system of claim 7 wherein the monolithic microcontroller includes memory for logging network activity based on frames received by the second network controller configured in the second mode, wherein the frames are transferred between the first network controller and the network media over the first set of one or more I/O terminals.

12. The microcontroller system of claim 7 wherein the monolithic microcontroller includes a DMA controller, wherein the DMA controller is operable to transfer information indicative of network activity, from the second network controller to memory.

13. A method of operating a monolithic microcontroller, the method comprising:

configuring a first network controller to operate either in a first mode for transferring frames to and from network media over a first set of one or more input/output (I/O) terminals or in a monitoring mode for logging network activity based on frames transferred between a second network controller and the network media over a second set of one or more I/O terminals, wherein the first network controller is different than the second network controller, and wherein logging network activity based on frames transferred between the second network controller and the network media comprises storing an indication of one more missed frames of information;

establishing a first path from the first network controller to the second set of one or more I/O terminals when the first network controller is configured in the monitoring mode, the first path not including the second network controller;

establishing a second path from the first network controller to the first set of one or more I/O terminals when the first network controller is configured in the first mode; and

wherein, while the first network controller is configured in the monitoring mode, saving, in the first network controller, each frame that is transferred between the second network controller and the network media over the second set of one or more I/O terminals.

14. The method of claim 13 further including transferring the saved frames for storage in memory.

15. The method of claim 14 including transferring the saved frames for storage in memory embedded in the microcontroller.

16. The method of claim 14 including transferring the saved frames for storage in memory external to the microcontroller.

17. The method of claim 14 including using the frames in memory to debug an application.

18. The method of claim 14 including setting a state of a multiplexor to provide the first or second path.

Assignments (18)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2013
From: ATMEL ROUSSET S.A.S
To: ATMEL CORPORATION
Reel/Frame 030181/0642 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2012
From: PEAN, GUILLAUME; SAMAT, PIERRE; YOUNES, SEBASTIEN
To: ATMEL ROUSSET S.A.S.
Reel/Frame 029134/0876 →
Continuity (1)
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