IP Library Granted Patent US 9,152,598
Granted Patent B2
US 9,152,598 · App. 13/687,044 · Granted Oct 6, 2015

Connecting multiple slave devices to a single master controller in bus system

Inventors: Francois Fosse (Nantes, FR); Laurent Le Goffic (Nantes, FR)
Assignee: Atmel Corporation
G06F13/4291G06F13/364
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Quick Facts
Patent No.
US 9,152,598
App. No.
13/687,044
Granted
Oct 6, 2015
Kind
B2
Abstract

A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state.

Claims (26)

1. A device comprising:

a bus master including a bi-directional data line and clock line and being configured to produce a select signal output for enabling data transmission on the bi-directional data line to first and second different data buses that support one or more slave devices, each slave device configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and

a de-multiplexer including an input and first and second outputs and a control input, the input being coupled to the bi-directional data line of the bus master, a first output of the de-multiplexer being coupled to the first data bus and a second output of the de-multiplexer being coupled to the second data bus, wherein the control input is configured to receive the select signal from the bus master;

wherein the bus master is configured to communicate to a first slave device coupled to the first data bus when the select signal is in a first state, and to communicate to a second different slave device coupled to the second data bus when the select signal is in a second different state.

2. The device of claim 1 wherein the bus master is an I2C master and the slave devices are I2C slaves.

3. The device of claim 1 wherein the bus master and the de-multiplexer are incorporated in a microcontroller.

4. The device of claim 1 wherein the select signal is provided on a general input/output port of the microcontroller.

5. The device of claim 1 wherein the slave devices have a same address.

6. The device of claim 1 wherein the de-multiplexer is a 1-2 de-multiplexer.

7. The device of claim 1 wherein the de-multiplexer is a 1-2 N de-multiplexer where N is an integer and wherein each output of the de-multiplexer is coupled to a data bus that in turn is coupled to one or more slave devices.

8. The device of claim 1 further comprising a second de-multiplexer including an input and first and second outputs and a control input, the input being coupled to the bi-directional clock line of the bus master, a first output of the second de-multiplexer being coupled to a first clock bus and a second output of the second de-multiplexer being coupled to a second clock bus, wherein the first and second clock buses are coupled to one or more slave devices associated with the first and second data buses respectively, and wherein the control input is configured to receive the select signal from the bus master.

9. The device of claim 3 further including logic for coupling the bus master and de-multiplexer.

10. A master device for communicating with two or more different slave devices over a single bus, the single bus including a data bus and a clock bus, an improvement comprising:

coupling the data bus from the master device to an input of a de-multiplexer and respective outputs of the de-multiplexer to different slave devices using different data buses; and

configuring the master device to control the de-multiplexer to select one of the different data buses associated with a respective one of the different slave devices depending upon which slave device is desired to be communicated with.

11. A microcontroller including:

a master device including a data line and clock line and being configured to produce a select signal output for enabling data transmission on the data line to first and second different data buses of the microcontroller that support one or more slave devices, each slave device configured to receive/transmit data over a respective data bus and to receive a clock signal from the master device from the clock line;

a de-multiplexer including an input and first and second outputs and a control input, the input being coupled to an output of the data line of the master device, a first output of the de-multiplexer being coupled to the first data bus and a second output of the de-multiplexer being coupled to the second data bus, and wherein the control input is configured to receive the select signal from the master device; and

logic coupling the master device, the de-multiplexer and output pads of the microcontroller that correspond to the first and second data buses;

wherein the master device is configured to communicate to a first slave device coupled to the first data bus when the select signal is in a first state, and to communicate to a second different slave device coupled to the second data bus when the select signal is in a second different state.

12. The microcontroller of claim 11 wherein the logic includes:

a first buffer coupling the first output of the de-multiplexer to a first pad associated with the first data bus of the microcontroller;

a second buffer coupling the second output of the de-multiplexer to a second pad associated with the second data bus of the microcontroller;

an AND gate having first and second inputs and an output coupled to an input of the data line of the master device;

a third buffer coupling the first pad of the microcontroller to the first input of the AND gate; and

a fourth buffer coupling the second pad of the microcontroller to the second input of the AND gate.

Assignments (18)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2013
From: FOSSE, FRANCOIS; GOFFIC, LAURENT LE
To: ATMEL NANTES SAS
Reel/Frame 030425/0547 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2013
From: ATMEL NANTES S.A.S.
To: ATMEL CORPORATION
Reel/Frame 030181/0767 →
Continuity (1)
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