Method of making ultrahigh density vertical NAND memory device
Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
1. A method of making a monolithic three dimensional NAND string, comprising:
forming a stack of alternating layers of a first layer and a second layer, wherein the first layer comprises a conductive or semiconductor control gate material, and wherein the second layer comprises an insulating sub-layer and a first sacrificial sub-layer;
etching the stack to form at least one opening in the stack;
selectively etching the first layer to form first recesses;
forming a blocking dielectric in the first recesses;
forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric;
forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening;
forming a semiconductor channel in the at least one opening;
etching the stack to expose a back side of the stack;
removing the first sacrificial sub-layer to form second recesses; and
forming a plurality of conductive or semiconductor shielding wings separated from each other in the second recesses;
wherein the first sacrificial sub-layer is located above or below the insulating sub-layer in each second layer.
2. The method of claim 1 , wherein each of the plurality of shielding wings is located between adjacent two of the plurality of discrete charge storage segments.
3. The method of claim 1 , wherein two of the plurality of shielding wings are located between adjacent two of the plurality of discrete charge storage segments.
4. The method of claim 1 , wherein:
the second layer further comprises a second sacrificial sub-layer; and
the insulating sub-layer is located between the first and second sacrificial sub-layers in each second layer.
5. The method of claim 4 , further comprising:
removing the first sacrificial sub-layer and the second sacrificial sub-layer to form second recesses and third recesses, respectively; and
forming a plurality of shielding wings separated from each other in the second and third recesses.
6. The method of claim 1 , wherein:
the semiconductor channel has a circular cross section when viewed from above; and
the step of forming the semiconductor channel in the at least one opening forms a semiconductor channel material on the side wall of the at least one opening but not in a central part of the at least one opening such that the semiconductor channel material does not completely fill the at least one opening and an insulating fill material is located in the central part of the at least one opening to completely fill the at least one opening.
7. The method of claim 1 , wherein:
the semiconductor channel has a circular cross section when viewed from above; and
the step of forming the semiconductor channel in the at least one opening completely fills the at least one opening with a semiconductor channel material.
8. The method of claim 1 , further comprising forming an upper electrode over the semiconductor channel and forming a lower electrode below the semiconductor channel prior to forming the stack of alternating layers.
9. The method of claim 1 , wherein the plurality of discrete charge storage segments comprise a plurality of discrete charge storage dielectric features or a plurality of floating gates.
10. The method of claim 1 , wherein:
the step of forming the blocking dielectric in the first recesses comprises forming a plurality of clam-shaped blocking dielectric segments in the first recesses between overhanging portions of the second material; and
the step of forming the plurality of discrete charge storage segments comprises forming each of the plurality of discrete charge storage segments inside an opening in a respective one of the plurality of clam-shaped blocking dielectric segments.
11. The method of claim 1 , further comprising:
providing at least one sacrificial feature over a substrate and below the stack of alternating layers; and
removing the at least one sacrificial feature to form a hollow region extending substantially parallel to a major surface of the substrate which connects the at least one openings and another opening in the stack to form a hollow U-shaped pipe space, prior to the step of forming the tunnel dielectric;
wherein the step of forming the semiconductor channel forms the semiconductor channel in the hollow U-shaped pipe space.