In-situ thermoelectric cooling
Methods and structures for thermoelectric cooling of 3D semiconductor structures are disclosed. Thermoelectric vias (TEVs) to form a thermoelectric cooling structure. The TEVs are formed with an etch process similar to that used in forming electrically active through-silicon vias (TSVs). However, the etched cavities are filled with materials that exhibit the thermoelectric effect, instead of a conductive metal as with a traditional electrically active TSV. The thermoelectric materials are arranged such that when a voltage is applied to them, the thermoelectric cooling structure carries heat away from the interior of the structure from the junction where the thermoelectric materials are electrically connected.
1. A semiconductor structure comprising:
a die comprised of a semiconductor material, and comprising a back-end-of-line wiring structure formed thereon;
a conductive region disposed within the die;
a first thermoelectric via (TEV) originating from a top surface of the semiconductor structure and terminating at the conductive region;
a second TEV originating from the top surface and terminating at the conductive region, wherein the first TEV and second TEV are disposed within the back-end-of-line wiring structure;
a first capture pad disposed on the top surface and connected to the first TEV; and
a second capture pad disposed on the top surface and connected to the second TEV.
2. The semiconductor structure of claim 1 , wherein the conductive region is comprised of copper.
3. The semiconductor structure of claim 1 , wherein the first TEV is filled with an n-type thermoelectric material comprising Bi 2 Te 3 .
4. The semiconductor structure of claim 1 , wherein the second TEV is filled with a p-type thermoelectric material comprising Bi 2 Se 3 .
5. The semiconductor structure of claim 1 , wherein the first TEV and second TEV are each lined with a barrier layer selected from the group consisting of tantalum and tantalum nitride.
6. The semiconductor structure of claim 1 , wherein the first capture pad and second capture pad are comprised of aluminum.
7. The semiconductor structure of claim 1 , wherein the first capture pad and second capture pad are comprised of a solder ball disposed on a ball-limiting-metallurgy structure.
8. A semiconductor structure comprising:
a first die, comprising a first back-end-of-line wiring structure formed thereon;
a second die disposed over the first die, the second die comprising a second back-end-of-line wiring structure formed thereon;
a thermoelectric cooler structure comprising:
a conductive region disposed within the first die;
a first thermoelectric via (TEV) extending from the conductive region, and traversing the second die, first back-end-of-line wiring structure, and second back-end-of-line wiring structure;
a second thermoelectric via (TEV) extending from the conductive region, and traversing the second die, first back-end-of-line wiring structure, and second back-end-of-line wiring structure;
a first capture pad disposed on the second die, and connected to the first TEV; and
a second capture pad disposed on the second die, and connected to the second TEV.
9. The semiconductor structure of claim 8 , wherein the conductive region is comprised of copper.
10. The semiconductor structure of claim 8 , wherein the first TEV is filled with an n-type thermoelectric material comprising Bi 2 Te 3 .
11. The semiconductor structure of claim 8 , wherein the second TEV is filled with a p-type thermoelectric material comprising Bi 2 Se 3 .
12. The semiconductor structure of claim 8 , wherein the first capture pad and second capture pad are comprised of aluminum.
13. The semiconductor structure of claim 8 , wherein the first capture pad and second capture pad are comprised of a solder ball disposed on a ball-limiting-metallurgy structure.
14. The semiconductor structure of claim 8 , further comprising a third die, the third die disposed on the second die, and wherein the first TEV and the second TEV traverse the third die.