Integrated circuit for remote keyless entry system
An integrated circuit for use in remote keyless entry (RKE) applications is disclosed that integrates two drivers with a shared dual mode antenna. The drivers may be integrated on a single integrated circuit chip using high voltage (HV) complementary metal-oxide-semiconductor (CMOS) processes. In immobilizer mode of operation, an immobilizer driver coupled to the dual mode antenna is configured to drive the dual mode antenna, while an LF mode driver coupled to the dual mode antenna is configured to be idle. In LF mode of operation, the LF mode driver is configured to drive the dual mode antenna, while the immobilizer driver is configured to be idle. In some implementations, the drivers are coupled to a common node coupled to the dual mode antenna and are selectively biased with different supply voltages based on the current mode of operation to prevent current leakage and component damage.
1. A circuit comprising:
a first driver having an input coupled to a supply voltage VDS and an output coupled to a common node, the first driver configured to drive a first signal at the common node during a first mode of operation, the first driver configured to reverse bias a first set of parasitic diodes of a first set of transistors of the first driver to prevent a current present at the common node from entering the first driver due to a second signal being present at the common node due to operation of a second driver during a second mode of operation;
a regulator coupled to the supply voltage VDS and configured to output a regulated supply voltage VTX during the second mode of operation; and
the second driver coupled in parallel with the first driver, the second driver having an input coupled to the regulator output and having an output coupled to the common node, the second driver configured to receive the voltage supply VDS during the first mode of operation and to receive the regulated supply voltage VTX during the second mode of operation, the second driver configured to drive the second signal at the common node during the second mode of operation, the second driver configured to reverse bias a second set of parasitic diodes of a second set of transistors of the second driver to prevent the current from entering the second driver due to the first signal being present at the common node due to operation of the first driver during the first mode of operation.
2. The circuit of claim 1 where during the first mode of operation VTX equals VDS.
3. The circuit of claim 1 , where during the second mode of operation VD S is greater or equal to VTX.
4. The circuit of claim 1 , where the regulator is bypassed during the first mode of operation.
5. The circuit of claim 1 , where during the first mode of operation the output of the second driver is kept in an ohmic state high enough to prevent leakage current from entering the second driver due to the first signal.
6. The circuit of claim 1 , where during the second mode of operation the output of the first driver is kept in an ohmic state high enough to prevent leakage current from entering the first driver due to the second signal.
7. The circuit of claim 1 , where the circuit is included in an integrated circuit chip installed in a vehicle.
8. The circuit of claim 1 , further comprising:
a booster coupled to a voltage supply and configured to output an unregulated supply voltage VDS that is higher than the voltage supply.
9. The circuit of claim 1 , further comprising:
a booster coupled to a voltage supply and configured to output a regulated supply voltage VDS that is higher than the voltage supply.
10. The circuit of claim 1 , where the circuit is configured for differential signals.
11. A method comprising:
providing a supply voltage VDS to a first driver having an output coupled to a common node, where VDS is higher than a voltage supply, the first driver configured to reverse bias a first set of parasitic diodes of a first set of transistors of the first driver to prevent a current present at the common node from entering the first driver due to a second signal being present at the common node due to operation of a second driver during a second mode of operation;
detecting a first mode of operation;
driving a first signal at the common node with the first driver during the first mode of operation;
detecting the second mode of operation;
providing a regulated supply voltage VTX to the second driver coupled in parallel to the first driver and having an output coupled to the common node; and
driving the second signal at the common node with the second driver, the second driver configured to reverse bias a second set of parasitic diodes of a second set of transistors of the second driver to prevent the current from entering the second driver due to the first signal being present at the common node due to operation of the first driver during the first mode of operation.
12. The method of claim 11 , where during the first mode of operation VTX equals VDS.
13. The method of claim 11 , where during the second mode of operation VDS is greater or equal to VTX.
14. The method of claim 11 , where the regulated supply voltage VTX is bypassed during the first mode of operation.
15. The method of claim 11 , where during the first mode of operation the output of the second driver is kept in an ohmic state high enough to prevent leakage current from entering the second driver due to the first signal.
16. The method of claim 11 , where during the second mode of operation the output of the first driver is kept in an ohmic state high enough to prevent leakage current from entering the first driver due to the second signal.
17. The method of claim 11 , further comprising regulating the supply voltage VDS.
18. A system comprising:
a dual mode antenna coupled to a common node;
a first driver having an input coupled to a supply voltage VDS and an output coupled to the common node, the first driver configured to drive the dual mode antenna during a first mode of operation, the first driver configured to reverse bias a first set of parasitic diodes of a first set of transistors of the first driver to prevent a current present at the common node from entering the first driver due to a second signal being present at the common node due to operation of a second driver during a second mode of operation;
a regulator coupled to the supply voltage VDS and configured to output a regulated supply voltage VTX during the second mode of operation; and
the second driver coupled in parallel with the first driver, the second driver having an input coupled to the regulator output and having an output coupled to the common node, the second driver configured to receive the voltage supply VDS during the first mode of operation and to receive the regulated supply voltage VTX during the second mode of operation, the second driver configured to drive the dual mode antenna during the second mode of operation, the second driver configured to reverse bias a second set of parasitic diodes of a second set of transistors of the second driver to prevent the current from entering the second driver due to the first signal being present at the common node due to operation of the first driver during the first mode of operation.
19. The system of claim 18 , where during the first mode of operation VTX equals VDS.
20. The system of claim 18 , where during the second mode of operation VDS is greater or equal to VTX.