Circuit and method for flicker suppression in light emitting diodes (LEDs)
View Patent ↗A circuit for flicker suppression in a Light Emitting Diode (LED) has a latch. The latch has a first state set with a trailing edge of Pulse Width Modulated Dimming (PWMD) pulse, and a second state set delayed with respect to the PWMD trailing edge. A trigger circuit is coupled to the latch. The trigger circuit sends a signal to the latch to change to the second state when a decision point occurs during a time following a duty limit D max of a gate of a LED driver circuit.
1. A circuit for flicker suppression in a Light Emitting Diode (LED) comprising:
a latch, the latch having a first state set with a trailing edge of Pulse Width Modulated Dimming (PWMD) pulse, and a second state set delayed with respect to the PWMD trailing edge; and
a trigger circuit coupled to the latch, the trigger circuit sending a signal to the latch to change to the second state when a decision point occurs during a time following a duty limit D max of a gate of a LED driver circuit, wherein the trigger circuit comprises: a plurality of logic gates, wherein the plurality of logic gates provides the signal to the latch to change to the second state when a decision point occurs during a time following a duty limit Dmax of a gate of a LED driver circuit; and a delay circuit coupled to at last one of the plurality of logic gates.
2. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 1 , wherein the trigger circuit has inputs coupled to a clock signal and the PWM pulse and an output coupled to the latch.
3. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 1 , wherein the trigger circuit comprises:
a plurality of logic gates; and
a delay circuit coupled to at last one of the plurality o logic gates.
4. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 1 , wherein the trigger circuit comprises:
a first logic gate having a first input coupled to a first output of the latch and a second input coupled to a PWM signal of the Led driver circuit;
a delay circuit coupled between the second input of the first logic gate and the PWM signal;
a second logic gate having a first input coupled to a second output of the latch and a second input coupled to the PWM signal of the Led driver circuit;
a third logic gate having a first input coupled to an output of the first logic gate and a second input coupled to an output of the second logic gate; and
a fourth logic gate having a first input coupled to an output of the third logic gate, a second input coupled to a clock signal; and an output coupled to an input of the latch.
5. A circuit for flicker suppression in a Light Emitting Diode (LED) comprising:
means for removing a duty cycle limit D max of a gate signal of an LED driver circuit past a decision point (DP) by terminating the gate signal upon meeting a reference signal sent to a comparator of the LED driver circuit, wherein the means comprises: a latch, the latch having a first state set with a trailing edge of Pulse Width Modulated Dimming (PWMD) pulse, and a second state set delayed with respect to the PWMD trailing edge; and a trigger circuit coupled to the latch, the trigger circuit sending a signal to the latch to change to the second state when a decision point occurs during a time following a duty limit Dmax of a gate of a LED driver circuit.
6. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 5 , wherein the trigger circuit has inputs coupled to a clock signal and the PWM pulse and an output coupled to the latch.
7. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 5 , wherein the trigger circuit comprises:
a plurality of logic gates; and
a delay circuit coupled to at last one of the plurality o logic gates.
8. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 5 , wherein the trigger circuit comprises:
a plurality of logic gates, wherein the plurality of logic gates provides the signal to the latch to change to the second state when a decision point occurs during a time following a duty limit D max of a gate of a LED driver circuit; and
a delay circuit coupled to at last one of the plurality o logic gates.
9. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 5 , wherein the trigger circuit comprises:
a first logic gate having a first input coupled to a first output of the latch and a second input coupled to a PWM signal of the Led driver circuit;
a delay circuit coupled between the second input of the first logic gate and the PWM signal;
a second logic gate having a first input coupled to a second output of the latch and a second input coupled to the PWM signal of the Led driver circuit;
a third logic gate having a first input coupled to an output of the first logic gate and a second input coupled to an output of the second logic gate; and
a fourth logic gate having a first input coupled to an output of the third logic gate, a second input coupled to a clock signal; and
an output coupled to an input of the latch.