Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
View Patent ↗A memory cell is provided that includes a reversible resistance-switching element above a substrate. The reversible resistance-switching element includes an etched material layer that includes an oxidized layer of the etched material layer above a non-oxidized layer of the etched material layer. Numerous other aspects are provided.
1. A memory cell comprising:
a reversible resistance-switching element above a substrate, the reversible resistance-switching element comprising an etched material layer that includes an oxidized layer of the etched material layer above a non-oxidized layer of the etched material layer.
2. The memory cell of claim 1 , wherein the etched material layer comprises one or more of Ta, TaN, Nb, NbN, Al, AlN, Hf, HfN, V, and VN.
3. The memory cell of claim 1 , wherein the reversible resistance-switching material comprises one or more of Ta 2 O 5 , Nb 2 O 5 , Al 2 O 3 , HfO 2 , and V 2 O 5 .
4. The memory cell of claim 1 , wherein the reversible resistance-switching element comprises an oxide thickness of about 500 angstroms or less.
5. The memory cell of claim 1 , wherein the reversible resistance-switching element comprises an oxide thickness of about 300 angstroms or less.
6. The memory cell of claim 1 , further comprising a steering element coupled to the reversible resistance-switching element.
7. The memory cell of claim 6 , wherein the steering element comprises a diode.
8. The memory cell of claim 6 , wherein the steering element comprises a polycrystalline diode.
9. The memory cell of claim 6 , wherein the steering element comprises a vertical polycrystalline diode.
10. The memory cell of claim 6 , wherein the steering element comprises a p-n diode or a p-i-n.
11. The memory cell of claim 6 , wherein the steering element and reversible resistance-switching element are coupled in series.
12. A memory cell comprising:
a first conductor above a substrate;
a reversible resistance-switching element above the first conductor, the reversible resistance-switching element comprising an etched material layer that includes an oxidized layer of the etched material layer above a non-oxidized layer of the etched material layer; and
a second conductor above the reversible resistance-switching element.
13. The memory cell of claim 12 , wherein the etched material layer comprises one or more of Ta, TaN, Nb, NbN, Al, AlN, Hf, HfN, V, and VN.
14. The memory cell of claim 12 , wherein the reversible resistance-switching material comprises one or more of Ta 2 O 5 , Nb 2 O 5 , Al 2 O 3 , HfO 2 , and V 2 O 5 .
15. The memory cell of claim 12 , wherein the reversible resistance-switching element comprises an oxide thickness of about 500 angstroms or less.
16. The memory cell of claim 12 , wherein the reversible resistance-switching element comprises an oxide thickness of about 300 angstroms or less.
17. The memory cell of claim 12 , wherein the memory cell further comprises a diode coupled to the reversible resistance-switching element.
18. The memory cell of claim 17 , wherein the diode and the reversible resistance-switching element are coupled in series.
19. The memory cell of claim 17 , wherein the diode comprises a vertical polycrystalline diode.
20. The memory cell of claim 19 , further comprising a silicide, silicide-germanide or germanide region in contact with polycrystalline material of the vertical polycrystalline diode, wherein the polycrystalline material is in a low-resistivity state.
21. A memory array comprising:
a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction;
a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction different from the first direction; and
a plurality of the memory cells of claim 1 , wherein each memory cell is disposed between one of the first conductors and one of the second conductors.
22. A monolithic three dimensional memory array comprising:
a first memory level formed above a substrate, the first memory level comprising a plurality of the memory cells of claim 1 ; and
a second memory level monolithically formed above the first memory level.
23. A memory array comprising:
a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction;
a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction different from the first direction; and
a plurality of the memory cells of claim 12 , wherein each memory cell is disposed between one of the first conductors and one of the second conductors.
24. A monolithic three dimensional memory array comprising:
a first memory level formed above a substrate, the first memory level comprising a plurality of the memory cells of claim 12 ; and
a second memory level monolithically formed above the first memory level.