Biological and chemical sensors
Device structures, fabrication methods, and design structures for a biological and chemical sensor used to detect a property of a substance. The device structure includes a drain and a source of a field effect transistor formed at a frontside of a substrate. A sensing layer is formed at a backside of the substrate. The sensing layer is configured to receive the substance.
1. A method of forming a sensor used to detect a property of a substance, the method comprising:
forming a drain and a source of a field effect transistor at a frontside of a substrate;
forming a sensing layer that is configured to receive the substance and that is located at a backside of the substrate opposite from the frontside of the substrate; and
forming a through silicon via (TSV) extending through the substrate and coupling the sensing layer with the field effect transistor,
wherein the TSV has a tip that projects outwardly from the backside of the substrate, and the sensing layer is formed at least partially on the tip of the TSV.
2. The method of claim 1 further comprising:
forming a recess at the backside of the substrate,
wherein the sensing layer is formed at least partially on the substrate in the recess.
3. The method of claim 2 further comprising;
forming a gate electrode of the field effect transistor at the frontside of the substrate.
4. The method of claim 3 wherein the TSV couples the sensing layer on the backside of the substrate with the gate electrode on the frontside of the substrate.
5. The method of claim 2 wherein the substrate is a semiconductor-on-insulator (SOI) wafer, the recess exposes a buried dielectric layer of the SOI wafer, and the sensing layer is at least partially positioned on the buried dielectric layer exposed by the recess.
6. The method of claim 5 wherein the drain and the source of the field effect transistor are formed in a device layer of the SOI wafer.
7. The method of claim 1 further comprising:
forming a gate electrode of the field effect transistor at the frontside of the substrate.
8. The method of claim 7 wherein the TSV couples the sensing layer on the backside of the substrate with the gate electrode on the frontside of the substrate.
9. The method of claim 1 further comprising:
forming a recess at the backside of the substrate,
wherein the tip of the TSV is positioned in the recess.
10. The method of claim 9 further comprising:
forming a portion of the sensing layer on a sidewall of the recess.
11. A device structure for a sensor used to detect a property of a substance, the device structure formed using a substrate having a frontside and a backside opposite from the frontside, and the device structure comprising:
a field effect transistor including a drain and a source at the frontside of the substrate;
a sensing layer located at the backside of the substrate, the sensing layer configured to receive the substance; and
a through silicon via (TSV) extending through the substrate and coupling the sensing layer with the field effect transistor,
wherein the TSV has a tip that projects outwardly from the backside of the substrate, and the sensing layer is positioned at least partially on the tip of the TSV.
12. The device structure of claim 11 further comprising:
a recess at the backside of the substrate,
wherein the sensing layer is located at least partially on the substrate in the recess.
13. The device structure of claim 12 further comprising;
a gate electrode of the field effect transistor at the frontside of the substrate.
14. The device structure of claim 13 the TSV couples the sensing layer at the backside of the substrate with the gate electrode at the frontside of the substrate.
15. The device structure of claim 12 wherein the substrate used to form the device structure is a semiconductor-on-insulator (SOI) wafer, the recess exposes a buried dielectric layer of the SOI wafer, and the sensing layer is positioned at least partially on the buried dielectric layer exposed by the recess.
16. The device structure of claim 15 wherein the drain and the source of the field effect transistor are formed in a device layer of the SOI wafer.
17. The device structure of claim 11 wherein the field effect transistor further includes a gate electrode at the frontside of the substrate.
18. The device structure of claim 17 wherein the TSV couples the sensing layer on the backside of the substrate with the gate electrode on the frontside of the substrate.
19. The device structure of claim 11 , wherein the substrate used to form the device structure is a semiconductor-on-insulator (SOI) wafer including a buried dielectric layer, and the tip projects from the buried dielectric layer outwardly from the backside of the substrate.
20. The device structure of claim 11 further comprising:
a recess at the backside of the substrate,
wherein the tip of the TSV is positioned in the recess.
21. The device structure of claim 20 wherein the substrate is a semiconductor-on-insulator (SOI) wafer including a buried dielectric layer and a handle wafer, the recess extends through the handle wafer to the buried dielectric layer, and the tip projects from the buried dielectric layer outwardly from the backside of the substrate.
22. The device structure of claim 21 wherein the recess includes a sidewall, and the sensing layer is at least partially positioned on the sidewall of the recess.
23. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a sensor used to detect a property of a substance, the HDL design structure comprising:
a field effect transistor including a drain and a source at the frontside of the substrate;
a sensing layer located at the backside of the substrate, the sensing layer configured to receive the substance; and
a through silicon via (TSV) extending through the substrate and coupling the sensing layer with the field effect transistor,
wherein the TSV has a tip that projects outwardly from the backside of the substrate, and the sensing layer is positioned at least partially on the tip of the TSV.
24. The HDL design structure of claim 23 wherein the HDL design structure comprises a netlist.
25. The HDL design structure of claim 23 wherein the DHL design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
26. The HDL design structure of claim 23 wherein the HDL design structure resides in a programmable gate array.