IP Library Granted Patent US 8,987,823
Granted Patent B2
US 8,987,823 · App. 13/771,255 · Granted Mar 24, 2015

Method and structure for forming a localized SOI finFET

Inventors: Kangguo Cheng (Schenectady, NY); Ali Khakifirooz (Mountain View, CA); Kern Rim (Yorktown Heights, NY); Ramachandra Divakaruni (Ossining, NY)
Assignee: International Business Machines Corporation
H01L27/1207H01L21/845
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Quick Facts
Patent No.
US 8,987,823
App. No.
13/771,255
Granted
Mar 24, 2015
Kind
B2
Abstract

Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed.

Claims (45)

1. A semiconductor structure comprising:

a semiconductor substrate;

a first set of fins formed on the semiconductor substrate;

a second set of fins formed on the semiconductor substrate;

an oxide region formed within the semiconductor substrate below the second set of fins;

a bulk-type fin diode formed on the first set of fins; and

a SOI-type finFET formed on the second set of fins.

2. The semiconductor structure of claim 1 , further comprising a planar region disposed on the semiconductor substrate.

3. The semiconductor structure of claim 1 , wherein the first set of fins are N-doped, and further comprising:

a p-doped semiconductor region disposed on the first set of fins;

a dielectric layer disposed over the second set of fins; and

a metal gate disposed over the dielectric layer.

4. The semiconductor structure of claim 3 , wherein the dielectric layer comprises hafnium oxide.

5. The semiconductor structure of claim 1 , wherein the first set of fins are P-doped, and further comprising:

an n-doped semiconductor region disposed on the first set of fins;

a dielectric layer disposed over the second set of fins; and

a metal gate disposed over the dielectric layer.

6. A semiconductor structure comprising:

a semiconductor substrate;

a first set of fins formed on the semiconductor substrate;

a second set of fins formed on the semiconductor substrate; and

an oxide region formed within the semiconductor substrate below the second set of fins;

a planar region disposed on the semiconductor substrate;

a bulk-type finFET formed on the first set of fins;

a SOI-type finFET formed on the second set of fins; and

a diode formed on the planar region.

7. A semiconductor structure comprising:

a semiconductor substrate;

a first set of fins formed on the semiconductor substrate;

a second set of fins formed on the semiconductor substrate, wherein the first set of fins and second set of fins have a fin width;

an oxide region formed within the semiconductor substrate below the second set of fins; and

a planar region disposed on the semiconductor substrate, wherein the planar region has a width ranging from 10 to 30 times larger than the fin width;

a bulk-type finFET formed on the first set of fins;

a SOI-type finFET formed on the second set of fins; and

a diode formed on the planar region.

8. The semiconductor structure of claim 7 , further comprising a second oxide region disposed within the semiconductor substrate between the planar region and the first set of fins.

9. A semiconductor structure comprising:

a semiconductor substrate;

a first set of fins formed on the semiconductor substrate;

a second set of fins formed on the semiconductor substrate, wherein the first set of fins and second set of fins have a fin width;

an oxide region formed within the semiconductor substrate below the second set of fins; and

a planar region disposed on the semiconductor substrate, wherein the planar region has a width ranging from 10 to 30 times larger than the fin width;

a bulk-type finFET formed on the first set of fins;

a SOI-type finFET formed on the second set of fins; and

a transistor formed on the planar region.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2013
From: CHENG, KANGGUO; DIVAKARUNI, RAMACHANDRA; KHAKIFIROOZ, ALI; RIM, KERN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 030111/0898 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2013
From: CHENG, KANGGUO; BASKER, VEERARAGHAVAN S.; DORIS, BRUCE B.; KHAKIFIROOZ, ALI; RIM, KERN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 029845/0340 →
Continuity (2)
Continuation In Part 13670768 · Nov 7, 2012
Related Publication 20140124863A1 · May 8, 2014