Method of fabricating a self-aligning damascene memory structure
View Patent ↗A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
1. A method of forming a memory cell, the method comprising:
forming a first pillar-shaped element comprising a first semiconductor material;
forming a first opening self-aligned with the first pillar-shaped element; and
depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element.
2. The method of claim 1 , wherein the first semiconductor material comprises N-type semiconductor material, and the second semiconductor material comprises P-type semiconductor material.
3. The method of claim 1 , wherein the first semiconductor material comprises P-type semiconductor material, and the second semiconductor material comprises N-type semiconductor material.
4. The method of claim 1 , wherein forming the first pillar shaped element comprises:
depositing the first semiconductor material over a substrate;
depositing a first sacrificial material over the first semiconductor material; and
patterning and etching the first sacrificial material and the first semiconductor material to form the first pillar shaped element.
5. The method of claim 4 , wherein the first sacrificial material comprises a dielectric material.
6. The method of claim 4 , wherein the first sacrificial material comprises Si 3 N 4 .
7. The method of claim 1 , wherein the first pillar-shaped element further comprises first sacrificial material, and wherein forming the first opening comprises:
depositing an insulating material on the first pillar-shaped element; and
removing the first sacrificial material to form the first opening.
8. The method of claim 7 , wherein the insulating material comprises one or more of silicon oxide, silicon dioxide, silicon oxynitride, and a high density plasma silicon dioxide.
9. The method of claim 1 , further comprising forming a second opening self-aligned with the second pillar shaped element.
10. The method of claim 9 , wherein forming the second opening comprises:
depositing a second sacrificial material over the second pillar shaped element;
patterning and etching the second sacrificial material to form rails of the second sacrificial material.
11. The method of claim 10 , further comprising:
depositing an insulating material on the rails of the second sacrificial material; and
removing the rails of the second sacrificial material to form the second opening.
12. The method of claim 11 , further comprising filling the second opening with conductive material to form a conductor.
13. The method of claim 9 , further comprising filling the second opening with a third semiconductor material.
14. The method of claim 13 , wherein the first semiconductor material comprises a heavily-doped N-type semiconductor material, the second semiconductor material comprises a lightly-doped N-type semiconductor material and the third semiconductor material comprises a heavily doped P-type semiconductor material.
15. The method of claim 13 , wherein the first semiconductor material comprises a heavily-doped P-type semiconductor material, the second semiconductor material comprises a lightly-doped N-type semiconductor material and the third semiconductor material comprises a heavily doped N-type semiconductor material.
16. A memory cell formed according to the method of claim 1 .
17. An array of memory cells formed according to the method of claim 1 .
18. A three-dimensional array of memory cells formed according to the method of claim 1 .