Delaying reset signals in a microcontroller system
A microcontroller system includes a reset delaying module that is configured to, during a power saving mode, receive and delay a reset signal from a reset source. The reset delaying module waits for a regulator ready signal from a voltage regulator because, prior to the reset signal, the voltage regulator is in a power saving mode. In response to receiving the regulator ready signal, the reset delaying module releases the reset, e.g., to a reset controller.
1. A microcontroller system comprising:
a reset controller;
a reset delaying module coupled to the reset controller; and
a reset source coupled to the reset delaying module;
wherein the reset delaying module is configured to perform operations comprising:
during a power saving mode, receiving a reset signal from the reset source;
delaying the reset signal at least partially based on duration of the reset signal;
waiting for a regulator ready signal from a voltage regulator; and
receiving the regulator ready signal and, in response to receiving the regulator ready signal, releasing the reset signal to the reset controller;
wherein the reset signal has a longer duration than a time between receiving the reset signal and receiving the regulator ready signal; and
wherein the reset signal has a shorter duration than a time between receiving the reset signal and receiving the regulator ready signal so that the reset delaying module is configured to delay the reset signal for longer than the duration of the reset signal.
2. The microcontroller system of claim 1 , wherein the voltage regulator is configured to provide a lower voltage during the power saving mode and a higher voltage on exiting the power saving mode, and wherein the voltage regulator is configured to provide a substantial fraction of the higher voltage after a regulator wakeup time has elapsed.
3. The microcontroller system of claim 2 , further comprising a processor coupled to the reset controller and a clock coupled to the processor, wherein the clock is frozen during the power saving mode so that the reset delaying module operates asynchronously, and wherein the clock is configured to provide a clock signal on exiting the power saving mode.
4. The microcontroller system of claim 3 , wherein the microcontroller is configured to enable the clock in response to receiving the regulator ready signal and the clock is configured to provide the clock signal after a clock wakeup time has elapsed.
5. The microcontroller system of claim 1 , wherein the reset delaying module comprises a delay chain coupled to a latch.
6. The microcontroller system of claim 5 , wherein the reset source is coupled to an input of the delay chain and an output of the delay chain is coupled to an input of the latch, and wherein an output of the latch is coupled to a plurality of logic gates coupled to the reset controller.
7. The microcontroller system of claim 6 , wherein the reset source is coupled to the plurality of logic gates and the regulator is coupled to the plurality of logic gates.
8. The microcontroller system of claim 1 , further comprising a plurality of additional reset sources and an additional reset delaying module for each additional reset source.
9. A method performed by a microcontroller, the method
comprising:
entering a power saving mode so that a voltage regulator is providing a lower voltage;
during the power saving mode, receiving a reset signal;
delaying the reset signal and exiting the power saving mode, including configuring the voltage regulator to provide a higher voltage higher than the lower voltage, wherein delaying the reset signal is at least partially based on a duration of the reset signal;
determining that the voltage regulator is providing at least a substantial fraction of the higher voltage and, in response, releasing the reset signal to a reset controller;
wherein the reset signal has a longer duration than a time between receiving the reset signal and determining that the voltage regulator is providing at least a substantial fraction of the higher voltage; and
wherein the reset signal has a shorter duration than a time between receiving the reset signal and determining that the voltage regulator is providing at least a substantial fraction of the higher voltage, so that delaying the reset signal comprises delaying the reset signal for longer than the duration of the reset signal.
10. The method of claim 9 , wherein determining that the voltage regulator is providing at least a substantial fraction of the higher voltage comprises receiving a ready signal from the voltage regulator.
11. The method of claim 9 , wherein delaying the reset signal comprises passing the reset signal through a delay chain coupled to a latch.
12. The method of claim 9 , wherein entering the power saving mode comprises freezing a clock, and wherein the method further comprises, in response to determining that the voltage regulator is providing at least a substantial fraction of the higher voltage, waking the clock.
13. The method of claim 12 , further comprising, after waking the clock, waiting for a wakeup time of the clock and then exiting the power saving mode.
14. The method of claim 9 , further comprising, after releasing the reset signal to the reset controller, propagating the reset signal to one or more digital modules.
15. The method of claim 14 , wherein entering the power saving mode comprises configuring the voltage regulator to have a lower output current capability, and wherein configuring the voltage regulator to provide a higher voltage further comprises configuring the voltage regulator to have a higher output current capability.
16. The method of claim 15 , wherein the one or more digital modules are configured to draw a current between the lower output current capability and the higher output current capability.