Proactive quality of service in multi-matrix system bus
A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.
1. An integrated circuit device, comprising:
a plurality of master bus devices coupled to a plurality of master bus layers;
a plurality of slave bus devices coupled to a plurality of slave bus layers;
a system bus matrix coupled to the plurality of master bus layers and the plurality of slave bus layers, the system bus matrix configured to dynamically route signals of the plurality of master bus layers to the plurality of slave bus layers, the system bus matrix including:
a plurality of decoders, each decoder of the plurality of decoders coupled to one of the plurality of master bus layers, and configured for decoding address signals received from the coupled master bus layer;
a plurality of arbiters, each arbiter of the plurality of arbiters coupled to each one of the plurality of decoders and configured to output a select signal based on results of an arbitration of transfer requests and quality of service signals generated by two or more master bus devices, wherein at least one downstream arbiter of the plurality of arbiters is configured to receive at least one of the quality of service signals from at least one upstream arbiter of the plurality of arbiters, and wherein the at least one downstream arbiter is configured to cause a transfer request generated by a first master bus device to inherit a quality of service signal for a pending transfer request generated by a second master bus device; and
a plurality of switches, each switch of the plurality of switches coupled to one arbiter of the plurality of arbiters and each one of the plurality of master bus layers, each one of the plurality of switches configured by one of the select signals to couple one of the plurality of master bus layers to one of the plurality of slave bus layers.
2. The device of claim 1 , where the transfer request and the quality of service signal entering the slave bus layer are generated by two different master bus devices.
3. The device of claim 1 , where each arbiter is configured to calculate a function of the transfer requests and quality of service signals, and output the select signal based on results of the calculating.
4. The device of claim 1 , where each arbiter is configured to continuously compare quality of service signals and output one of the quality of service signals that encodes a highest priority value relative to the other quality of service signals.
5. The device of claim 3 , where the quality control service signal that is output is associated with a pending transfer request.
6. The device of claim 1 , where the master bus layers and slave bus layers include address, data and control signals, and the control signals include the quality of service signals.
7. The device of claim 1 , where the quality of service signals are generated by master bus devices and are encoded with current levels of urgency of the master bus devices to perform data transfers.
8. The device of claim 1 , where the current level of urgency is categorized as a latency sensitive data transfer or a bandwidth sensitive data transfer.
9. The device of claim 1 , where the integrated circuit is a microcontroller.
10. An integrated circuit device, comprising:
a plurality of master bus layers;
a plurality of slave bus layers; and
a system bus matrix coupled to the plurality of master bus layers and the plurality of slave bus layers, the system bus matrix configured to route dynamically a transfer request and a quality of service signal from a master bus layer to a slave bus layer, wherein a downstream arbiter in the system bus matrix is configured to receive the quality of service signal from an upstream arbiter, and wherein the transfer request is generated by a first master bus device in the master bus layer and the quality of service signal is generated by a second master bus device in the master bus layer and the downstream node is configure to cause the transfer request to inherit the quality of service signal.
11. The device of claim 10 , where the transfer request and the quality of service signal are generated by different master bus devices coupled to different master bus layers.
12. The device of claim 10 , where the quality of service signal is associated with a pending transfer request of a master bus device coupled to the master bus layer.
13. The device of claim 10 , where the master bus layers and slave bus layers include address, data and control signals, and the control signals include quality of service signals.
14. The device of claim 10 , where the quality of service signal is encoded with a current level of urgency of a master bus device to perform a data transfer.
15. The device of claim 10 , where the current level of urgency is categorized as a latency sensitive data transfer or a bandwidth sensitive data transfer.
16. The device of claim 10 , where a master bus device changes the routed quality of service signal and the change is propagated to the slave bus layer independent of the routed transfer request.
17. The device of claim 10 , where the integrated circuit is a microcontroller.
18. A method comprising:
receiving, in system bus matrix of a microcontroller, two or more transfer requests and corresponding quality of service signals; and
dynamically routing one of the transfer requests and one of the quality of service signals to a slave bus layer based on arbitration of the transfer requests and quality of service signals, where the routed transfer request and quality of service signals are generated by different master bus devices, a downstream arbiter in the system bus matrix is configured to receive the quality of service signals from an upstream arbiter, the transfer request is generated by a first master bus device in the master bus layer and the quality of service signal is generated by a second master bus device in the master bus layer and the downstream node is configure to cause the transfer request to inherit the quality of service signal.
19. The method of claim 18 , where each of the quality of service signals is encoded with a current level of urgency of one of the master bus devices to perform data transfer.
20. The method of claim 19 , where each of the quality of service signals is associated with a pending transfer request of one of the master bus devices.