Combined power supply and input/output system with boost capability
A combined power and input/output system for an electronic device includes a host system; a target system operably coupled to the host system via a combined power and I/O line; and a power boost circuit in the target system for enabling a higher voltage target device.
1. A combined power and input/output system, comprising:
a host system operable to drive a high voltage and a low voltage on a combined power and I/O line;
a target system operably coupled to the host system via the combined power and I/O line; and
a power boost circuit in the target system coupled with the combined power and I/O line and operable to convert the high voltage supplied on the combined power and I/O line to a voltage higher than the high voltage, wherein the higher voltage is stored on a power supply capacitor, wherein the power boost circuit comprises an inductor and a diode interposed between the host system and the power supply capacitor on the combined power and I/O line; and
a switching system operable in cooperation with the power boost circuit to charge and discharge the inductor into the power supply capacitor during communication when said combined power and I/O line is at the high voltage.
2. The combined power and input/output system of claim 1 , wherein a maximum communication baud rate is synchronized to an on period of the power boost circuit.
3. The combined power and input/output system of claim 1 , further comprising a software override of the power boost circuit.
4. The combined power and input/output system of claim 1 , wherein during an input phase the power boost circuit is asserted for a predetermined period after a rising edge of a data bit.
5. The combined power and input/output system of claim 1 , wherein during an output phase, the power boost circuit is asserted for an entirety of a high portion of a data bit.
6. The combined power and input/output system according to claim 1 , further comprising a switch within the target system arranged between the power supply capacitor and the combined power and I/O line.
7. The combined power and input/output system according to claim 6 , wherein the switch is controlled by a tri-state driver whose input is connected with the combined power and I/O line, whose output controls the switch and whose tristate control is connected with the power supply capacitor.
8. The combined power and input/output system according to claim 6 , wherein the switch is a field effect transistor controlled by a further field effect transistor coupled between a gate of the field effect transistor and ground, wherein a gate of the further field effect transistor is connected with the combined power and I/O line.
9. The target system according to claim 1 , further comprising a boost control unit receiving a feedback signal from the power supply capacitor and controlling the switching system, wherein the boost control unit comprises an enable input.
10. A method for providing power and I/O on a single line, comprising:
driving a combined I/O power line by a host to charge a power supply capacitor of a target system in a first mode;
alternately connecting and disconnecting a power boost circuit to charge and discharge the power supply capacitor when driving the combined I/O power line during a communication over the combined I/O power line in a second mode, wherein the power supply capacitor is charged to voltage higher than a voltage provided by the host.
11. A method for providing power and I/O on a single line in accordance with claim 10 , wherein during data input of the target system, the power boost circuit is asserted so as to charge the power supply capacitor responsive to a rising edge of a data bit transmitted by the host.
12. A method for providing power and I/O on a single line in accordance with claim 10 , wherein during data output of the target system, the power boost circuit is asserted for an entire high portion of a data bit.
13. A method for providing power and I/O on a single line in accordance with claim 10 , further comprising employing a software control of the power boost circuit to provide power during a high current activity.
14. An electronic device, comprising:
a host system operable to drive a high voltage and a low voltage on a combined power and I/O line;
a target system operably coupled to the host system via the combined power I/O line;
wherein the target system includes a power boost circuit coupled with the combined power and input/output line and receiving a high voltage signal via the combined power I/O line and a switching system wherein the power boost circuit and switching system are configured to allow the host system to charge a power supply capacitor on the target system in a first mode to a voltage higher than the high voltage, and alternately charge and discharge the power supply capacitor during a communication via the combined power I/O line in a second mode, wherein the alternately charging and discharging is in synchronization with said communication.
15. An electronic device in accordance with claim 14 , wherein the switching system comprises a tristate device.
16. An electronic device in accordance with claim 14 , wherein the switching system comprises a switching transistor.
17. An electronic device in accordance with claim 14 , wherein during data input of the second mode, the power boost circuit is asserted so as to charge the power supply capacitor responsive to a rising edge of a data bit.
18. An electronic device in accordance with claim 14 , wherein during data output of the second mode, the power boost circuit is asserted for an entire high portion of a data bit.
19. An electronic device in accordance with claim 14 , further comprising a software input for the power boost circuit to provide power during a high current activity.