Digital-to-analog-converter with resistor ladder
A digital-to analog-converter (DAC) has a MSB resistor ladder with a plurality of series connected resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential, a LSB resistor ladder with a plurality of series connected resistors, and a plurality of switching units for connecting one of the series connected resistors of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit has a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein each switch is configured form a resistor of similar value of the resistors of the LSB resistor ladder when switched on.
1. A digital-to analog-converter (DAC) comprising:
an MSB resistor ladder comprising a plurality of series connected MSB resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential;
a partial LSB resistor ladder comprising a plurality of series connected resistors; and
a plurality of switching units for connecting at least one of said series connected MSB resistors of the MSB resistor ladder with the partial LSB resistor ladder, wherein each switching unit comprises a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the partial LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the partial LSB resistor ladder and wherein a switch path of each switch is configured to form a resistor and wherein when said first and second switches are turned on, the first switch, the partial LSB resistor ladder and the second switch form an LSB resistor ladder connected in a parallel with the associated MSB resistor.
2. The digital-to analog-converter according to claim 1 , further comprising a decoder for controlling one of the switching units to connect an associated MSB resistor of the MSB resistor ladder with the partial LSB resistor ladder and for selecting one of a plurality of tapping nodes of the LSB resistor ladder for providing an output voltage of the DAC.
3. The digital-to analog-converter according to claim 2 , wherein each tapping node is coupled with an output of the LSB resistor ladder by an N-channel field effect transistor.
4. The digital-to analog-converter according to claim 1 , wherein each first and second switch of the plurality of switching units is formed by a p-channel depletion field effect transistor.
5. The digital-to analog-converter according to claim 4 , wherein the partial LSB resistor ladder is formed by a plurality of p-channel depletion transistors connected as diodes.
6. The digital-to analog-converter according to claim 5 , wherein the partial LSB resistor ladder is formed by a plurality of sub LSB resistor ladders coupled in series.
7. The digital-to analog-converter according to claim 6 , wherein each switching unit has a first and a second output connected with the first and second switch, respectively and further comprises a third switch for directly connecting the second terminal of an associated MSB resistor with a third output, wherein the first of the sub LSB resistor ladders is connected with the first output and the last of the sub LSB resistor ladders is connected with the second and third output.
8. The digital-to analog-converter according to claim 7 , wherein the third switch is an N-channel field effect transistor.
9. The digital-to analog-converter according to claim 8 , wherein each of the sub LSB resistor ladders comprises 2 q resistors except for the last sub LSB resistor ladder which comprises 2 q -2 resistors and wherein the last LSB resistor ladder comprises a direct connection between a third input connected with the third output of the switching unit and a LSB resistor ladder output, wherein q is a positive integer.
10. The digital-to analog-converter according to claim 9 , wherein q=3.
11. The digital-to analog-converter according to claim 1 , wherein the MSB resistor ladder comprises 2 p resistors and an effective LSB resistor ladder formed by a switching unit and the LSB resistor ladder comprises 2 m resistors.
12. The digital-to analog-converter according to claim 11 , wherein p=32 and m=128.
13. The digital-to analog-converter according to claim 1 , wherein the first reference potential is one half of a supply voltage and the second reference potential is ground.
14. The digital-to analog-converter according to claim 13 , wherein the first reference potential is provided by a reference resistor ladder coupled in series with the MSB resistor ladder.
15. The digital-to analog-converter according to claim 14 , further comprising compensation circuits for each resistor of the reference resistor ladder.
16. The digital-to analog-converter according to claim 1 , further comprising a compensation circuit for each resistor of the MSB resistor ladder.
17. The digital-to analog-converter according to claim 16 , wherein each compensation circuit is controlled depending on a MSB input value.
18. A method of generating an analog voltage from a digital value comprising the steps of:
providing an MSB resistor ladder comprising a plurality of series connected resistors between a first and second reference potential;
providing a partial LSB resistor ladder comprising a plurality of series connected resistors;
depending on an MSB value selectively connecting a first terminal of a selected MSB resistor with a first terminal of the partial LSB resistor ladder by a first switch and connecting second terminal of the selected MSB resistor with a second terminal of the partial LSB resistor ladder by a second switch, wherein a switch path of each switch is configured to form a resistor and wherein when said first and second switches are turned on, the first switch, the partial LSB resistor ladder and the second switch form an LSB resistor ladder connected in parallel with the selected MSB resistor; and
depending on an LSB value selecting a tapping node of the LSB resistor ladder to provide an analog output voltage.
19. The method according to claim 18 , wherein each tapping node is coupled with an output of the LSB resistor ladder by an N-channel field effect transistor.
20. The method according to claim 18 , wherein each first and second switch of the plurality of switching units is formed by a p-channel depletion field effect transistor.
21. The method according to claim 20 , wherein the partial LSB resistor ladder is formed by a plurality of p-channel depletion transistors connected as diodes.
22. The method according to claim 21 , wherein the partial LSB resistor ladder is formed by a plurality of sub LSB resistor ladders coupled by series.
23. The method according to claim 18 , wherein the first reference potential is one half of a supply voltage and the second reference potential is ground.
24. The method according to claim 23 , further comprising providing the first reference potential by a reference resistor ladder coupled in series with the MSB resistor ladder.
25. The method according to claim 24 , further comprising compensating each resistor of the reference resistor ladder.
26. The method to claim 18 , further comprising compensating each resistor value of the MSB resistor ladder depending on the MS value.