Multi-chip antenna diversity picture-in-picture architecture
View Patent ↗A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.
1. A multi-chip antenna diversity architecture for mobile television that supports Picture-in-Picture (PIP), said multi-chip antenna diversity architecture comprising:
a first receiver chip that receives a first program data that includes a first program ID (PID) set, said first receiver chip comprising:
a crystal;
a crystal oscillator circuit operatively connected to said crystal, wherein said crystal oscillator circuit generates a clock signal based on a frequency of said crystal;
a crystal oscillator clock buffer operatively connected to said crystal oscillator circuit, wherein said crystal oscillator clock buffer receives said clock signal from said crystal oscillator circuit; and
a diversity transmitter that transmits said first program data composed of said first program ID (PID) set;
a second receiver chip that receives second program data that includes a second program ID (PID) set, said second receiver chip comprising:
a clock phase locked loop (PLL) that receives said clock signal from said crystal oscillator clock buffer;
a decoder that decodes said second program data;
a diversity receiver that receives said first program data from said diversity transmitter, wherein said diversity receiver does not receive a reference clock signal from said diversity transmitter and wherein said crystal does not directly transmit a signal to said second receiver chip; and
a Picture-in-Picture (PIP) combiner that combines said first program data received from said diversity receiver with said second program data received from said decoder to generate a combined PIP data stream, wherein said PIP combiner comprises a PID comparison module that compares said first PID set of said first program data with said second PID set of said second program data to detect an occurrence of a common PID.
2. The multi-chip antenna diversity architecture of claim 1 , wherein said PIP combiner transmits said combined PIP data stream to a host processor.
3. The multi-chip antenna diversity architecture of claim 1 , wherein said PIP combiner comprises a PID generation module that generates a new PID when said PID comparison module detects an occurrence of said common PID.
4. The multi-chip antenna diversity architecture of claim 3 , wherein said PIP combiner comprises a PID remapping module that remaps said common PID to said new PID.
5. The multi-chip antenna diversity architecture of claim 1 , wherein said first program data and said second program data comprise audio/video data.
6. The multi-chip antenna diversity architecture of claim 1 , wherein said first program data and said second program data comprise non-audio/video data.
7. A multi-chip antenna diversity architecture comprising:
a first receiver chip that receives a first program data comprising a first program ID (PID) set, wherein said first receiver chip comprises:
a crystal oscillator that generates a clock signal;
a crystal oscillator clock buffer that receives said clock signal; and
a diversity transmitter that transmits said first program data comprising said first PID set;
a second receiver chip that receives second program data comprising a second PID set, wherein said second receiver chip comprises:
a clock phase locked loop (PLL) that receives said clock signal;
a decoder that decodes said second program data;
a diversity receiver that receives said first program data from said diversity transmitter, wherein said diversity receiver does not receive a reference clock signal from said diversity transmitter and wherein said crystal does not directly transmit a signal to said second receiver chip; and
a Picture-in-Picture (PIP) combiner that combines said first program data received from said diversity receiver with said second program data received from said decoder to generate a combined PIP data stream, wherein said PIP combiner comprises a PID comparison module that compares said first PID set of said first program data with said second PID set of said second program data to detect an occurrence of a common PID.
8. The multi-chip antenna diversity architecture of claim 7 , wherein said PIP combiner transmits said combined PIP data stream to a host processor.
9. The multi-chip antenna diversity architecture of claim 7 , wherein said PIP combiner comprises a PID generation module that generates a new PID when said PID comparison module detects an occurrence of said common PID.
10. The multi-chip antenna diversity architecture of claim 9 , wherein said PIP combiner comprises a PID remapping module that remaps said common PID to said new PID.
11. The multi-chip antenna diversity architecture of claim 7 , wherein said first program data and said second program data comprise audio/video data.
12. The multi-chip antenna diversity architecture of claim 7 , wherein said first program data and said second program data comprise non-audio/video data.