Capacitor backup for SRAM
Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.
1. A Static Random Access Memory (SRAM) device, comprising:
one or more SRAM cells, each SRAM cell including:
a first and a second CMOS inverter that are cross-coupled;
a feedback switch coupled to an output of the first CMOS inverter and an input of the second CMOS inverter; and
a capacitive backup circuit, not in a feedback circuit formed by the first and the second CMOS inverter, coupled to the output of the feedback switch, the backup circuit including:
a capacitor; and
a backup switch configured in a series connection between the capacitor and the feedback switch and configured to selectively isolate the capacitor from the feedback circuit.
2. The SRAM device of claim 1 , further comprising one or more pass switches on the SRAM cell coupled to a word bit line and the input of the second CMOS inverter.
3. The SRAM device of claim 1 , further comprising a read circuit on the SRAM cell coupled to the output of the second inverter.
4. The SRAM device of claim 1 , wherein a beta ratio for second CMOS inverter is biased.
5. The SRAM device of claim 1 , wherein the capacitor is an eDRAM trench capacitor.
6. The SRAM device of claim 5 , wherein the capacitor is coupled to a resistor in series.
7. An SRAM device, comprising:
one or more SRAM cells, each SRAM cell having cross-coupled inverters that are configured and arranged to hold a memory state;
a capacitive backup circuit having at least one capacitive element, the capacitive backup circuit configured and arranged to:
store a backup copy of the memory state in response to an activation of a backup switch and a deactivation of an input voltage; and
provide the backup copy of the memory state in response to the deactivation of a feedback switch, activation of the backup switch, and the deactivation of the input voltage.
8. The SRAM device of claim 5 , wherein the capacitive element is an eDRAM trench capacitor.
9. The SRAM device of claim 5 , wherein a first inverter from the cross-coupled inverters is stronger than a second inverter from the cross-coupled inverters.
10. The SRAM device of claim 9 , wherein the first inverter is stronger than a write bit line driver.
11. The SRAM device of claim 9 , wherein a beta ratio of the second inverter is biased.
12. The SRAM device of claim 5 , wherein the SRAM cell includes a read circuit.
13. The SRAM device of claim 5 , wherein the SRAM cell includes a feedback switch.