Selecting memory cells using source lines
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.
1. A memory device comprising:
memory cells arranged in rows and columns; and
source lines associated with memory sections, wherein a memory section includes a plurality of memory cells,
wherein source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section,
wherein for an erase operation of the first memory section:
the first source line is configured to provide a first voltage while source lines for the other memory sections on the same row are configured to provide a second voltage that is different from the first voltage, and
a wordline and a sense gate line corresponding to the first memory section are configured to provide non-zero voltages while wordlines and sense gate lines corresponding to memory sections in other rows are configured to provide zero voltage.
2. The memory device of claim 1 , wherein a memory section includes a plurality of consecutive memory cells arranged in a row, forming a memory group.
3. The memory device of claim 2 , wherein the memory section includes at least eight consecutive memory cells arranged in a row, and wherein the memory group includes at least one of a memory byte or a memory word.
4. The memory device of claim 1 , wherein the memory device is configured to operate without byte select transistors for controlling the memory sections.
5. The memory device of claim 1 , wherein the first source line is common for all memory sections that are included in a same column of the memory device as the first memory section.
6. The memory device of claim 1 , wherein the first source line is common for a subset of memory sections that are included in a same column of the memory device as the first memory section.
7. The memory device of claim 6 , wherein each column of the memory device includes a plurality of subsets of memory sections, each subset of memory sections associated with a source line that is different from source lines associated with other subsets of memory sections.
8. The memory device of claim 1 , wherein each row of memory cells is selectable by a same wordline and each column of memory cells is selectable by a same bitline.
9. The memory device of claim 8 , wherein a memory cell includes a select transistor and a sense transistor,
the select transistor comprising:
a gate terminal coupled to gate terminals of select transistors in other memory cells in a same row to form a wordline, and
a drain terminal coupled to drain terminals of select transistors in other memory cells in a same column to form a bitline; and
the sense transistor comprising:
a gate terminal coupled to gate terminals of sense transistors in other memory cells in the same row to form a sense gate line, and
a source terminal configured as the source of the memory cell.
10. The memory device of claim 9 , wherein for a write operation of a first memory cell included in the first memory section, a wordline and a bitline corresponding to the first memory cell are configured to provide non-zero voltages, while a sense gate line corresponding to the first memory cell is configured to provide zero voltage, and
wherein other wordlines and sense gate lines corresponding to memory sections in other rows are configured to provide zero voltage.
11. The memory device of claim 10 , wherein the write operation is independent of voltages provided by the first source line and source lines corresponding to the other memory sections.
12. The memory device of claim 1 , wherein the memory device comprises an Electrically Erasable Programmable Read-Only Memory (EEPROM).
13. A system comprising:
a memory device comprising:
memory cells arranged in rows and columns; and
source lines associated with memory sections, wherein a memory section includes a plurality of memory cells,
wherein source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section, and
wherein gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals; and
instructions stored in a non-transitory machine-readable medium for execution by a processor and configured to cause the processor to perform operations comprising:
selecting the first memory section for an erase operation by providing a preset first voltage on the first source line while providing a preset second voltage different from the first voltage on the source lines for the other memory sections on the same row; and
providing preset non-zero voltages on a wordline and a sense gate line, respectively, corresponding to the first memory section, while providing zero voltage on other wordlines and sense gate lines corresponding to memory sections in other rows of the memory device.
14. The system of claim 13 , wherein a memory section includes a plurality of consecutive memory cells arranged in a row, forming a memory group.
15. The system of claim 14 , wherein the memory section includes at least eight consecutive memory cells arranged in a row, and wherein the memory group includes at least one of a memory byte and a memory word.
16. The system of claim 13 , wherein the memory device is configured to operate without byte select transistors for controlling the memory sections.
17. The system of claim 13 , wherein the first source line is common for all memory sections that are included in a same column of the memory device as the first memory section.
18. The system of claim 13 , wherein the first source line is common for a subset of memory sections that are included in a same column of the memory device as the first memory section.
19. The system of claim 18 , wherein each column of the memory device includes a plurality of subsets of memory sections, each subset of memory sections associated with a source line that is different from source lines associated with other subsets of memory sections.
20. The system of claim 13 , wherein each row of memory cells in the memory device is selectable by a same wordline and each column of memory cells is selectable by a same bitline.
21. The system of claim 20 , wherein a memory cell in the memory device includes a select transistor and a sense transistor, the select transistor comprising:
a gate terminal coupled to gate terminals of select transistors in other memory cells in a same row to form a wordline, and
a drain terminal coupled to drain terminals of select transistors in other memory cells in a same column to form a bitline; and
the sense transistor comprising:
a gate terminal coupled to gate terminals of sense transistors in other memory cells in the same row to form a sense gate line, and
a source terminal configured as the source of the memory cell.
22. The system of claim 21 , wherein the instructions are configured to cause the processor to perform operations comprising:
selecting a first memory cell included in the first memory section for a write operation by providing preset non-zero voltages on a wordline and a bitline corresponding to the first memory cell while providing zero voltage on a sense gate line corresponding to the first memory cell; and
providing zero voltage on other wordlines and sense gate lines corresponding to memory sections in other rows.
23. The system of claim 22 , wherein the write operation is independent of voltages provided by the first source line and source lines corresponding to the other memory sections.
24. The system of claim 13 , wherein the memory device comprises an Electrically Erasable Programmable Read-Only Memory (EEPROM).
25. The memory device of claim 1 , wherein gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.