Erase for 3D non-volatile memory with sequential selection of word lines
An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.
1. A method for performing an erase operation for a string of storage elements in a 3D stacked non-volatile memory device, comprising:
pre-charging a channel of the string by applying a pre-charge voltage to one end of the string, the string comprises a plurality of selected storage elements; and
subsequently, erasing each selected storage element by applying an erase voltage, higher than the pre-charge voltage, to the one end of the string to charge the channel higher while configuring control gate voltages of the selected storage elements to encourage erasing of the selected storage elements in respective erase periods, wherein a start time of each respective erase period is based on a position of the selected storage element in the string.
2. The method of claim 1 , wherein:
the start time and a duration of each respective erase period are based on the position of the selected storage element in the string.
3. The method of claim 1 , wherein:
for each selected storage element, the start time is later when a distance along the string of the selected storage element from the one end of the string is greater.
4. The method of claim 3 , wherein:
the start times increase by progressively smaller increments as the distances along the string of the selected storage elements from the one end of the string become greater.
5. The method of claim 1 , wherein:
for each selected storage element, a duration of the respective erase period is greater when a distance along the string of the selected storage element from the one end of the string is greater.
6. The method of claim 5 , wherein:
the respective erase periods increase by progressively smaller increments as the distances along the string of the selected storage elements from the one end of the string become greater.
7. The method of claim 1 , wherein:
the applying the pre-charge voltage to the one end of the string charges the channel by gate-induced drain leakage of a select gate at the one end of the string.
8. The method of claim 7 , wherein:
for each selected storage element, the respective start time is based on a time at which a region of the channel directly beneath the selected storage element is expected to reach a predetermined voltage.
9. The method of claim 1 , wherein:
the control gate voltages which are configured to encourage erasing of the selected storage elements are at a voltage which is sufficiently low compared to a voltage in the channel to induce tunneling of holes from the channel into charge trapping regions of the selected storage elements.
10. The method of claim 1 , wherein:
the configuring the control gate voltages to encourage erasing comprises driving the control gate voltages lower from a floating level to a reduced level.
11. The method of claim 10 , further comprising:
for each selected storage element, at an end of the respective erase period, driving the control gate voltage higher from the reduced level to a level which discourages erasing of the selected storage elements, the level which discourages erasing of the selected storage elements is sufficiently high compared to a voltage in the channel to discourage tunneling of holes from the channel into charge trapping regions of the selected storage elements.
12. The method of claim 1 , wherein:
the selected storage elements are arranged in progressively larger groups in a direction moving away from the one end of the string, each group having a common start time.
13. The method of claim 1 , wherein:
the string is U-shaped and comprises a drain side which terminates at the one end of the string, a source side which terminates at another end of the string and a back gate which joins the drain side and the source side;
the pre-charging the channel of the string comprises applying the pre-charge voltage to another end of the string; and
the erasing each selected storage element comprises applying the erase voltage to the another end of the string.
14. The method of claim 1 , wherein:
the configuring the control gate voltages to encourage erasing comprises driving the control gate voltages lower from a driven level to a reduced level.
15. A three-dimensional stacked non-volatile memory device, comprising:
a string comprising a plurality of selected storage elements; and
one or more control circuits, the one or more control circuits, to perform an erase operation for the string are configured to:
pre-charge a channel of the string by application of a pre-charge voltage to one end of the string, and
then erase each selected storage element by application of an erase voltage, higher than the pre-charge voltage, to the one end of the string to charge the channel higher, and by configuration of control gate voltages of the selected storage elements which encourage erase of the selected storage elements in respective erase periods, wherein a start time of each respective erase period is based on a position of the selected storage element in the string.
16. The three-dimensional stacked non-volatile memory device of claim 15 , wherein:
the start time and a duration of each respective erase period are based on the position of the selected storage element in the string.
17. The three-dimensional stacked non-volatile memory device of claim 15 , wherein:
for each selected storage element, the start time is later when a distance along the string of the selected storage element from the one end of the string is greater.
18. The three-dimensional stacked non-volatile memory device of claim 15 , wherein:
for each selected storage element, a duration of the respective erase period is greater when a distance along the string of the selected storage element from the one end of the string is greater.
19. The three-dimensional stacked non-volatile memory device of claim 15 , wherein:
the application of the pre-charge voltage to the one end of the string charges the channel by gate-induced drain leakage of a select gate at the one end of the string.
20. The three-dimensional stacked non-volatile memory device of claim 15 , wherein:
the control gate voltages which are configured to encourage erasing of the selected storage elements are at a voltage which is sufficiently low compared to a voltage in the channel to induce tunneling of holes from the channel into charge trapping regions of the selected storage elements.
21. The three-dimensional stacked non-volatile memory device of claim 15 , wherein:
the one or more control circuits, to configure the control gate voltages to encourage erasing, are configured to drive the control gate voltages lower from a floating level to a reduced level.
22. The three-dimensional stacked non-volatile memory device of claim 15 , wherein:
the one or more control circuits, to configure the control gate voltages to encourage erasing, are configured to drive the control gate voltages lower from a driven level to a reduced level.
23. A method for performing an erase operation for a string of storage elements in a three-dimensional stacked non-volatile memory device, comprising:
pre-charging a channel of the string by applying a pre-charge voltage to one end of the string, the string comprises a plurality of selected storage elements; and
subsequently, applying an erase voltage, higher than the pre-charge voltage, to the one end of the string to charge the channel higher while driving control gate voltages of the selected storage elements to a reduced level to encourage erasing of the selected storage elements in respective erase periods, and for each selected storage element, at an end of the respective erase period, driving the control gate voltage higher from the reduced level to a level which discourages erasing of the selected storage elements, wherein a duration of each respective erase period is based on a position of the selected storage element in the string.
24. The method of claim 23 , wherein:
the control gate voltages which are configured to encourage erasing of the selected storage elements are at a voltage which is sufficiently low compared to a voltage in the channel to induce tunneling of holes from the channel into charge trapping regions of the selected storage elements.
25. The method of claim 23 , further comprising:
the level which discourages erasing of the selected storage elements is sufficiently high compared to a voltage in the channel to discourage tunneling of holes from the channel into charge trapping regions of the selected storage elements.
26. The method of claim 1 , wherein:
a duration of each respective erase period is based on the position of the selected storage element in the string; and
the selected storage elements are arranged in progressively larger groups in a direction moving away from the one end of the string, each group having a common duration.
27. A three-dimensional stacked non-volatile memory device, comprising:
a string comprising a plurality of selected storage elements; and
one or more control circuits, the one or more control circuits, to perform an erase operation for the string:
pre-charge a channel of the string by application of a pre-charge voltage to one end of the string, and
erase each selected storage element by application of an erase voltage, higher than the pre-charge voltage, to the one end of the string to charge the channel higher, and by configuration of control gate voltages of the selected storage elements which encourage erase of the selected storage elements in respective erase periods, wherein a duration of each respective erase period is based on a position of the selected storage element in the string.