Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
View Patent ↗A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.
1. A method of forming a memory cell, the method comprising:
forming a diode above a substrate; and
forming a material layer on the substrate;
patterning and etching the material layer; and
oxidizing the patterned and etched material layer to form a reversible resistance-switching material.
2. The method of claim 1 , wherein the material layer comprises one or more of Ta, TaN, Nb, NbN, Al, AIN, Hf, HfN, V, and VN.
3. The method of claim 1 , wherein the reversible resistance-switching material comprises one or more of Ta 2 O 5 , Nb 2 O 5 , Al 2 O 3 , Hf 0 2 , and V 2 O 5 .
4. The method of claim 1 , wherein forming the diode comprises forming a polycrystalline diode.
5. The method of claim 1 , wherein forming the diode comprises forming a vertical polycrystalline diode.
6. The method of claim 1 , wherein forming the diode comprises forming a p-n diode or a p-i-n diode.
7. The method of claim 1 , wherein the reversible resistance-switching element has an oxide thickness of about 500 angstroms or less.
8. The method of claim 1 , wherein the reversible resistance-switching element has an oxide thickness of about 300 angstroms or less.
9. The method of claim 1 , further comprising coupling the steering element and reversible resistance-switching element in series.
10. A memory cell formed according to the method of claim 1 .
11. A method of forming a memory cell, the method comprising:
forming a first conductor above a substrate;
forming a material layer on the substrate;
patterning and etching the material layer; and
oxidizing the patterned and etched material layer to form a reversible resistance-switching material;
forming a diode above the first conductor; and
forming a second conductor above the diode and the reversible resistance-switching element.
12. The method of claim 11 , wherein the material layer comprises one or more of Ta, TaN, Nb, NbN, Al, AIN, Hf, HfN, V, and VN.
13. The method of claim 11 , wherein the reversible resistance-switching material comprises one or more of Ta 2 O 5 , Nb 2 O 5 , Al 2 0 3 , HfO 2 , and V 2 O 5 .
14. The method of claim 11 , wherein forming the diode comprises forming a vertical polycrystalline diode.
15. The method of claim 14 , further comprising forming a silicide, silicide-germanide or germanide region in contact with polycrystalline material of the vertical polycrystalline diode so that the polycrystalline material is in a low-resistivity state.
16. The method of claim 11 , wherein the reversible resistance-switching element has an oxide thickness of about 500 angstroms or less.
17. The method of claim 11 , wherein the reversible resistance-switching element has an oxide thickness of about 300 angstroms or less.
18. The method of claim 11 , further comprising coupling the diode and the reversible resistance-switching element in series.
19. A memory cell formed according to the method of claim 11 .
20. A monolithic three dimensional memory array comprising:
a first memory level formed above a substrate, the first memory level comprising a plurality of memory cells, each memory cell formed according to the method of claim 1 ; and
at least a second memory level monolithically formed above the first memory level.
21. A monolithic three dimensional memory array comprising:
a first memory level formed above a substrate, the first memory level comprising a plurality of memory cells, each memory cell formed according to the method of claim 11 ; and
at least a second memory level monolithically formed above the first memory level.