Peripheral registers with flexible data width
View Patent ↗A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.
1. A method comprising:
receiving a read transfer request to read data from a register of a peripheral component coupled to a bus;
determining that the request indicates a subsize access of the register;
asserting one or more of a plurality of strobe signals on the bus to indicate that a portion of the register has valid data to be read, wherein the plurality of strobe signals indicate byte lanes to use during a read transfer on the bus; and
transferring the valid data over the bus.
2. The method of claim 1 , where the portion is less than a maximum width of the register.
3. The method of claim 1 , where the bus is compliant with AMBA Peripheral Bus (APB) protocol.
4. The method of claim 2 , where an address offset for the register is based on the maximum register width.
5. The method of claim 4 , where the maximum register width is one of 8, 16 or 32 bits.
6. The method of claim 1 , where the data transfer is completed in one bus operation.
7. A method comprising:
receiving a read transfer request to read data from a register of a peripheral component coupled to a bus;
determining that the request indicates a supersize access of the register;
asserting two or more strobe signals of a plurality of strobe signals on the bus to indicate that two or more registers have valid data, wherein the plurality of strobe signals indicate byte lanes to use during a read transfer on the bus; and
transferring the data over the bus.
8. The method of claim 7 , where the bus is compliant with AMBA Peripheral Bus (APB) protocol.
9. The method of claim 7 , where an address offset for each register is based on a maximum register width.
10. The method of claim 9 , where each maximum register width is one of 8, 16 or 32 bits.
11. The method of claim 7 , where the data transfer is performed in one bus operation.
12. A circuit comprising:
a master;
a slave;
a bus coupling the master to the slave, the circuit configured for:
receiving a read transfer request to read data from a register of the slave;
determining that the request indicates a subsize access of the register;
asserting one or more of a plurality of strobe signals on the bus to indicate that a portion of the register has valid data to be read, wherein the plurality of strobe signals indicate byte lanes to use during a read transfer on the bus; and
transferring the valid data over the bus.
13. The circuit of claim 12 , where the portion is less than a maximum width of the register.
14. The circuit of claim 12 , where the bus is compliant with AMBA Peripheral Bus (APB) protocol.
15. The circuit of claim 13 , where an address offset for the register is based on the maximum register width.
16. The circuit of claim 15 , where the maximum register width can be one of 8, 16or 32 bits.
17. The circuit of claim 12 , where the data is transferred in a single bus operation.
18. A circuit comprising:
a master;
a slave;
a bus coupling the master to the slave, the circuit configured for:
receiving a read transfer request to read data from a register of a peripheral component coupled to a bus;
determining that the request indicates a supersize access of the register;
asserting two or more strobe signals of a plurality of strobe signals on the bus to indicate that two or more registers have valid data, wherein the plurality of strobe signals indicate byte lanes to use during a read transfer on the bus; and
transferring the data over the bus.
19. The circuit of claim 18 , where the bus is compliant with AMBA Peripheral Bus (APB) protocol.
20. The circuit of claim 18 , where an address offset for each register is based on a maximum register width.
21. The circuit of claim 20 , where each maximum register width is one of 8, 16 or 32 bits.
22. The circuit of claim 18 , where the data transfer is performed in one bus operation.