Centralized peripheral access protection
View Patent ↗Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.
1. A system comprising:
one or more peripheral components;
a centralized peripheral access controller; and
a bus coupling together the centralized peripheral access controller and the one or more peripheral components, where the centralized peripheral access controller is configured to:
determine whether data associated with a peripheral component indicates that access to the peripheral component is locked or unlocked; and
allow access to the peripheral component if the data indicates that access is unlocked and deny access to the peripheral component if the data indicates that access is locked,
wherein the centralized peripheral access controller includes a register comprising one or more bits that are configured to indicate lock statuses of the one or more peripheral components.
2. The system of claim 1 , where the data is one or more bits that can be set or cleared by software to lock or unlock access to the peripheral component.
3. The system of claim 1 , where the centralized peripheral access controller is further configured to allow a write operation to the peripheral component in a debug mode.
4. The system of claim 1 , where the centralized peripheral access controller is further configured to allow direct memory access (DMA) to the peripheral component.
5. The system of claim 1 , where the centralized peripheral access controller is configured to not allow locking of a locked peripheral component.
6. The system of claim 1 , where the centralized peripheral access controller is configured to not allow unlocking of an unlocked peripheral component.
7. The system of claim 1 , where the bus is compliant with AMBA Advanced Peripheral Bus (APB) protocol.
8. A method comprising:
receiving, at a centralized peripheral controller in an integrated circuit (IC), a request to access a peripheral component;
determining whether data associated with the peripheral component indicates that access is locked or unlocked, wherein the centralized peripheral controller configures one or more bits in a register to indicate lock statuses of one or more peripheral components; and
allowing access to the peripheral component if the data indicates that access to the peripheral component is unlocked and denying access to the peripheral component if the data indicates that access to the peripheral component is locked.
9. The method of claim 8 , where the data is one or more bits that can be set or cleared by software to lock or unlock access to the peripheral component.
10. The method of claim 8 , further comprising:
allowing, by the centralized peripheral controller, a write operation to the peripheral component in a debug mode.
11. The method of claim 8 , further comprising:
allowing, by the centralized peripheral controller, direct memory access (DMA) to the peripheral component.
12. The method of claim 8 , further comprising:
not allowing, by the centralized peripheral controller, locking of a locked peripheral component.
13. The method of claim 8 , further comprising:
not allowing, by the centralized peripheral controller, unlocking of an unlocked peripheral component.
14. The method of claim 8 , where a bus couples the centralized peripheral controller to the peripheral component, and where the bus is compliant with AMBA Advanced Peripheral Bus (APB) protocol.
15. A microcontroller device comprising:
one or more peripheral components;
a centralized peripheral access controller that is coupled to the one or more peripheral components through a bus, wherein the centralized peripheral access controller is configured to:
determine whether data associated with a peripheral component indicates that access to the peripheral component is locked or unlocked;
conditioned on determining that the data indicates that access is unlocked, allow access to the peripheral component; and
conditioned on determining that the data indicates that access is locked, deny access to the peripheral component,
wherein the centralized peripheral access controller includes a register comprising one or more bits that are configured to indicate lock statuses of the one or more peripheral components.
16. The microcontroller device of claim 15 , wherein each bit in the register corresponds to a different peripheral component and indicates a lock status of the corresponding peripheral component.
17. The microcontroller device of claim 15 , where the data includes one or more bits that can be set or cleared by software to lock or unlock access to the peripheral component.
18. The microcontroller device of claim 15 , where the centralized peripheral access controller is further configured to allow at least one of a write operation to the peripheral component in a debug mode, or direct memory access (DMA) to the peripheral component.
19. The microcontroller device of claim 15 , where the centralized peripheral access controller is configured to disallow at least one of locking of a locked peripheral component, or unlocking of an unlocked peripheral component.
20. The microcontroller device of claim 15 , where the bus is compliant with AMBA Advanced Peripheral Bus (APB) protocol.