Dense finFET SRAM
A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features.
1. A semiconductor device, comprising:
a plurality of fins formed on a semiconductor substrate having a plurality of pitches; and
a plurality of devices formed across two or more of the plurality of fins, the plurality of devices including a first device including merged fins with an epitaxial material along a majority of a sidewall of the merged fins, and a second device including unmerged fins.
2. The semiconductor device as recited in claim 1 , wherein the plurality of devices form an SRAM cell.
3. The semiconductor device as recited in claim 1 , wherein the first device includes at least one of a pull down device and a pass gate device.
4. The semiconductor device as recited in claim 1 , wherein the second device includes a pull up device.
5. The semiconductor device as recited in claim 1 , wherein the merged fins include merged sources and/or drains.
6. The semiconductor device as recited in claim 1 , wherein the plurality of pitches includes a first pitch of 20 nm and a second pitch of 30 nm.