IP Library Granted Patent US 9,595,456
Granted Patent B2
US 9,595,456 · App. 13/971,619 · Granted Mar 14, 2017

Wafer manufacturing cleaning apparatus, process and method of use

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Quick Facts
Patent No.
US 9,595,456
App. No.
13/971,619
Granted
Mar 14, 2017
Kind
B2
Abstract

A cleaning wafer or substrate for use in cleaning, or in combination with, components of, for example, integrated chip manufacturing apparatus. The cleaning substrate can include a substrate having varying predetermined surface features, such as one or more predetermined adhesive, non-tacky, electrostatic, projection, depression, or other physical sections. The predetermined features can provide for more effective cleaning of the components with which they are used, such as an integrated chip manufacturing apparatus in the place of the integrated chip wafer. The cleaning substrate can be urged into cleaning or other position by vacuum, mechanical, electrostatic, or other forces. The cleaning substrate can adapted to accomplish a variety of functions, including abrading or polishing. The cleaning substrate may be made by a novel method of making, and it may then be used in a novel method of use I combination with chip manufacturing apparatus.

Claims (27)

1. An uncompressed integrated chip manufacturing apparatus cleaning wafer of the type useable to clean an integrated chip manufacturing apparatus, the uncompressed integrated chip manufacturing apparatus cleaning wafer comprising a resilient cleaning pad having a first cleaning side and a second side, the first cleaning side including:

a predetermined first tacky cleaning section on the first cleaning side having a predetermined first thickness and predetermined level of tack; and

a predetermined compressible tack-free first protrusion

(a) adjacent the predetermined first tacky cleaning section, and

(b) having a predetermined first protrusion thickness thicker than the predetermined first thickness, said predetermined compressible tack-free first protrusion projecting farther away from the first cleaning side than the predetermined first tacky cleaning section and when compression is released providing predetermined first means for reducing contact between the predetermined first cleaning section and a portion of the semiconductor wafer manufacturing apparatus.

2. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 1 wherein the first cleaning side includes a predetermined second tacky cleaning section, with a predetermined second level of tack, the predetermined first level tack being predetermined to be different than the predetermined second level of tack.

3. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 1 also having a predetermined second protrusion

(a) adjacent the predetermined first tacky cleaning section, and

(b) having a predetermined second protrusion thickness thicker than the predetermined first thickness, said predetermined second protrusion thickness providing predetermined second means for urging the predetermined first cleaning section away from contact with the or another portion of the semi-conductor wafer manufacturing apparatus.

4. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 2 also having a predetermined second protrusion

(a) adjacent the predetermined first tacky cleaning section,

(b) having a predetermined second protrusion thickness thicker than the predetermined first thickness, and

(c) having predetermined compressibility, said predetermined second protrusion thickness providing predetermined second means for urging the predetermined first cleaning section away from contact with the or another portion of the semi-conductor wafer manufacturing apparatus upon decompression of the predetermined second protrusion.

5. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 1 having a predetermined abrasive surface section including predetermined abrasive filler.

6. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 2 having a predetermined abrasive surface section including predetermined abrasive filler.

7. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 3 having a predetermined abrasive surface section including predetermined abrasive filler.

8. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 4 having a predetermined abrasive surface section including predetermined abrasive filler.

9. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 1 including a predetermined edge exclusion at a predetermined edge of the uncompressed integrated chip manufacturing apparatus cleaning wafer.

10. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 2 including a predetermined edge exclusion at a predetermined edge of the uncompressed integrated chip manufacturing apparatus cleaning wafer.

11. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 3 including a predetermined edge exclusion at a predetermined edge of the uncompressed integrated chip manufacturing apparatus cleaning wafer.

12. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 4 including a predetermined edge exclusion at a predetermined edge of the uncompressed integrated chip manufacturing apparatus cleaning wafer.

13. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 5 including a predetermined edge exclusion at a predetermined edge of the uncompressed integrated chip manufacturing apparatus cleaning wafer.

14. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 6 including a predetermined edge exclusion at a predetermined edge of the uncompressed integrated chip manufacturing apparatus cleaning wafer.

15. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 7 including a predetermined edge exclusion at a predetermined edge of the uncompressed integrated chip manufacturing apparatus cleaning wafer.

16. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 8 including a predetermined edge exclusion at a predetermined edge of the uncompressed integrated chip manufacturing apparatus cleaning wafer.

17. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 1 wherein the second side includes a predetermined second side tacky cleaning section.

18. The uncompressed integrated chip manufacturing apparatus cleaning wafer of claim 2 wherein the second side includes a predetermined second side tacky cleaning section.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2023
From: INTERNATIONAL TEST SOLUTIONS, LLC
To: ENTEGRIS, INC.
Reel/Frame 065764/0493 →
SECURITY INTEREST Recorded Jul 8, 2022
From: CMC MATERIALS, INC.; INTERNATIONAL TEST SOLUTIONS, LLC; QED TECHNOLOGIES INTERNATIONAL, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 060615/0001 →
SECURITY INTEREST Recorded Jul 8, 2022
From: ENTEGRIS, INC.; ENTEGRIS GP, INC.; POCO GRAPHITE, INC.; CMC MATERIALS, INC.; INTERNATIONAL TEST SOLUTIONS, LLC; QED TECHNOLOGIES INTERNATIONAL, INC.
To: TRUIST BANK, AS NOTES COLLATERAL AGENT
Reel/Frame 060613/0072 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2022
From: JPMORGAN CHASE BANK, N.A.
To: CABOT MICROELECTRONICS CORPORATION; QED TECHNOLOGIES INTERNATIONAL, INC.; FLOWCHEM LLC; KMG ELECTRONIC CHEMICALS, INC.; KMG-BERNUTH, INC.; MPOWER SPECIALTY CHEMICALS LLC; SEALWELD (USA), INC.; INTERNATIONAL TEST SOLUTIONS, LLC; CMC MATERIALS, INC.
Reel/Frame 060592/0260 →
CHANGE OF NAME Recorded May 3, 2021
From: INTERNATIONAL TEST SOLUTIONS, INC.
To: INTERNATIONAL TEST SOLUTIONS, LLC
Reel/Frame 056121/0757 →
SECURITY AGREEMENT Recorded Apr 30, 2021
From: INTERNATIONAL TEST SOLUTIONS, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 056104/0979 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2021
From: HUMPHREY, ALAN E.; DUVALL, JAMES H.; BROZ, JERRY J.
To: INTERNATIONAL TEST SOLUTIONS, INC.
Reel/Frame 055500/0329 →