Breaking code execution based on time consumption
An on-chip system uses a time measurement circuit to trap code that takes longer than expected to execute by breaking code execution on excess time consumption.
1. A method of breaking code execution based on time consumption performed by an integrated circuit (IC) device, the method comprising:
receiving a first signal indicating a start point defined in source code, the first signal generated when the start point is executed by the IC device;
starting a counter in a time measurement circuit in response to receiving the first signal;
counting, using an interrupt level counter coupled to the counter, interrupt levels for nested interrupt signals;
receiving a second signal indicating a stop point defined in the source code, the second signal generated when the stop point is executed by the IC device;
stopping the counter in the time measurement circuit in response to receiving the second signal; and
generating a program break or time event based on a comparison of time measured by the time measurement circuit with a maximum and minimum time setting.
2. The method of claim 1 , further comprising:
comparing, using a comparator coupled to the counter, the count from the counter to a count representing the maximum or the minimum time setting; and
generating a signal indicating a program break or time event.
3. The method of claim 1 , where the IC device is a microcontroller.
4. The method of claim 1 , where the start and stop points are defined in the source code by code instrumentation.
5. The method of claim 1 , where the start and stop points are defined in the source code by instruction fetch address comparators.
6. The method of claim 1 , further comprising:
comparing, using a first comparator coupled to the counter, the count from the counter to a count representing the maximum time setting, the first comparator generating a signal indicating a program break or maximum time event; and
comparing, using a second comparator coupled to the counter, the count from the counter to a count representing the minimum time setting, the second comparator generating a signal indicating a program break or minimum time event.
7. An integrated circuit (IC) device including a system for breaking code execution based on time consumption, the system comprising:
a time measurement circuit including a counter, the time measurement circuit configured to start and stop the counter based on signals indicative of start and stop points defined in the code, the signals generated while compiled source code is executing on the IC device, where the time measurement circuit further comprises:
a first comparator coupled to the counter and configured for comparing the count from the counter to a count representing a maximum time setting, the first comparator generating a signal indicating a program break or maximum time event; and
a second comparator coupled to the counter and configured for comparing the count from the counter to a count representing a minimum time setting, the second comparator generating a signal indicating a program break or minimum time event; and
a debug or event system coupled to the time measurement circuit and configured to generate a program break or time event, respectively, based on a comparison of time measured by the time measurement circuit with the maximum and the minimum time setting.
8. The system of claim 7 , where the IC device is a microcontroller.
9. The system of claim 7 , where the start and stop points are defined in the source code by code instrumentation.
10. The system of claim 7 , where the start and stop points are defined in the source code by instruction fetch address comparators.
11. The system of claim 7 , where the time measurement circuit further comprises:
a first comparator coupled to the counter and configured for comparing the count from the counter to a count representing the maximum time setting, the first comparator generating a signal indicating a program break or maximum time event; and
a second comparator coupled to the counter and configured for comparing the count from the counter to a count representing the minimum time setting, the second comparator generating a signal indicating a program break or minimum time event.
12. The system of claim 7 , further comprising:
an interrupt level counter coupled to the counter and configured to count interrupt levels for nested interrupt signals.
13. An integrated circuit (IC) device including a system for breaking code execution based on time consumption, the system comprising:
a time measurement circuit including a counter, the time measurement circuit configured to start and stop the counter based on signals indicative of start and stop points defined in the code, the signals generated while compiled source code is executing on the IC device, where the start and stop points are defined in the source code by instruction fetch address comparators; and
a debug or event system coupled to the time measurement circuit and configured to generate a program break or time event, respectively, based on a first comparison of time measured by the time measurement circuit with a maximum time setting and a second comparison of time measured by the time measurement circuit with a minimum time setting.
14. The system of claim 13 , where the time measurement circuit further comprises:
a comparator coupled to the counter and configured for:
comparing the count from the counter to a count representing the maximum or minimum time setting; and
generating a signal indicating a program break or time event.
15. The system of claim 13 , further comprising:
an interrupt level counter coupled to the counter and configured to count interrupt levels for nested interrupt signals.
16. The system of claim 13 , where the IC device is a microcontroller.
17. The system of claim 13 , where the start and stop points are defined in the source code by code instrumentation.
18. The system of claim 13 , where the time measurement circuit further comprises:
a first comparator coupled to the counter and configured for comparing the count from the counter to a count representing the maximum time setting, the first comparator generating a signal indicating a program break or maximum time event; and
a second comparator coupled to the counter and configured for comparing the count from the counter to a count representing the minimum time setting, the second comparator generating a signal indicating a program break or minimum time event.
19. The system of claim 13 , wherein at least one of the maximum time setting or the minimum time setting is preconfigured by a user.