Method for obtaining a palladium surface finish for copper wire bonding on printed circuit boards and IC-substrates
View Patent ↗The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an IC-substrate, possessing a layer assembly comprising a copper bonding portion and a palladium or palladium alloy layer and a substrate having a copper wire bonded to aforementioned layer assembly.
1. A method for forming a copper wire on a substrate, said substrate having at least one wire bonding portion made of copper or copper alloy comprising the steps of
(i) providing a substrate having at least one wire bonding portion made of copper or copper alloy;
(ii) forming a palladium layer on the at least one wire bonding portion, wherein the palladium is deposited from an electroless (autocatalytic) plating palladium bath comprising
a palladium ion source;
a complexing agent;
a reducing agent
and wherein the palladium content is more than 99.9 wt-%;
and thereafter
(iii) bonding a copper wire onto the palladium layer.
2. The method according to claim 1 , wherein the palladium layer according to step (ii) is formed directly upon the copper or copper alloy bonding portion.
3. The method according to claim 1 , wherein the palladium layer has a thickness of 0.05-5.0 μm.
4. The method according to claim 1 , wherein the palladium layer has a thickness of 0.1-0.5 μm.
5. The method according to claim 1 , wherein the reducing agent is formic acid or a salt thereof.
6. The method according to claim 1 , wherein copper wire is a pure copper or copper alloy wire which is coated with gold or palladium layer.
7. The method according to claim 6 , wherein the palladium or gold layer coating has a thickness of between 5-50 nm.
8. The method according to claim 1 , wherein prior to step (ii) the at least one wire bonding portion is activated by immersing it into a solution containing palladium ions.
9. A layer assembly comprising
(i) at least one wire bonding portion layer made of copper or copper alloy; and directly deposited thereon
(ii) a palladium layer having a thickness of 0.05-0.5 μm and having a palladium content of more than 99.9 wt-%; and
(iii) a copper wire bonded onto the palladium layer.
10. A printed circuit board possessing a layer assembly according to claim 9 further comprising a soldering portion for connecting external parts with the printed circuit board.
11. An integrated circuit possessing a layer assembly according to claim 9 .
12. A method for forming a layer assembly, the layer assembly comprising:
(i) at least one wire bonding portion layer made of copper or copper alloy; and directly deposited thereon
(ii) a palladium layer having a thickness of 0.05-0.5 μm and having a palladium content of more than 99.9 wt-%; and
(iii) a copper wire bonded onto the palladium layer;
the method comprising:
(i) providing a substrate having the at least one wire bonding portion made of copper or copper alloy;
(ii) forming the palladium layer on the at least one wire bonding portion, wherein the palladium is deposited from an electroless (autocatalytic) plating palladium bath comprising
a palladium ion source;
a complexing agent;
a reducing agent
and wherein the palladium content is more than 99.9 wt-%;
and thereafter
(iii) bonding the copper wire onto the palladium layer.
13. The method according to claim 12 , wherein prior to step (ii) the at least one wire bonding portion is activated by immersing it into a solution containing palladium ions.
14. A printed circuit board possessing a layer assembly formed according to the method of claim 12 further comprising a soldering portion for connecting external parts with the printed circuit board.
15. An integrated circuit possessing a layer assembly formed according to the method of claim 12 .