Methods of forming FinFET semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices
One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of a plurality of source/drain regions and, with the replacement gate structure in position, forming at least one source/drain contact structure for each of the plurality of source/drain regions, wherein the at least one source/drain contact structure is conductively coupled to a portion of the metal silicide layer and a dimension of the at least one source/drain contact structure in a gate width direction of the transistor is less than a dimension of the source/drain region in the gate width direction.
1. A method of forming a FinFET transistor above an active region defined in a semiconductor substrate, comprising:
forming a plurality of fins in said semiconductor substrate;
forming a sacrificial gate structure above said plurality of fins, said sacrificial gate structure extending in a gate width direction oriented perpendicular with respect to an axial length direction of said plurality of fins;
forming a sidewall spacer adjacent said sacrificial gate structure;
performing an epitaxial deposition fin-merger process to form a plurality of merged-fin regions from portions of said plurality of fins that define a plurality of source/drain regions for said transistor;
removing said sacrificial gate structure to define a gate recess;
forming a conductive replacement gate structure in said gate recess;
forming a dielectric cap layer above said conductive replacement gate structure in said gate recess;
after forming said replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of said plurality of source/drain regions;
forming a first sacrificial layer of material above said source/drain regions;
performing at least one etching process to define a patterned first sacrificial layer of material that comprises features that correspond to said at least one source/drain contact structure and to remove at least portions of said dielectric gate cap layer and at least a portion of said sidewall spacer so as to thereby expose a portion of said conductive replacement gate structure;
forming a layer of insulating material around said patterned first sacrificial layer of material and in contact with said exposed portion of said replacement gate structure;
with said replacement gate structure in position, removing remaining portions of said first sacrificial layer of material so as to defined a plurality of source/drain contact opening in said layer of insulating material exposing portions of said metal silicide layer; and
forming at least one source/drain contact structure for each of said plurality of source/drain regions in said plurality of source/drain contact openings, wherein said at least one source/drain contact structure is formed such that it is conductively coupled to a portion of said metal silicide layer and a dimension of said at least one source/drain contact structure in said gate width direction is less than a dimension of said source/drain region in said gate width direction.
2. The method of claim 1 , further comprising forming a gate contact structure that is conductively coupled to said replacement gate structure.
3. The method of claim 2 , wherein said at least one source/drain contact structure and said gate contact structure are formed at the same time by performing a plurality of common process operations.
4. The method of claim 1 , further comprising:
forming a second sacrificial material in said source/drain contact openings;
removing said second sacrificial material from within said source/drain contact openings so as to thereby expose said metal silicide layer; and
after removing said second sacrificial material, forming said at least one conductive structure in each of said source/drain contact openings such that it is conductively coupled to said metal silicide layer.
5. The method of claim 4 , wherein, after forming said second sacrificial material in said source/drain contact openings but prior to removing said second sacrificial material from within said source/drain contact openings, the method further comprises:
masking said second sacrificial material;
with said second sacrificial material masked, forming a gate contact opening in said layer of insulating material to expose a portion of said replacement gate structure; and
after removing said second sacrificial material from within said source/drain contact openings, performing a plurality of common process operations to form said at least one source/drain contact structure in said source/drain contact openings and a gate contact structure in said gate contact opening at the same time.
6. The method of claim 4 , wherein said first sacrificial layer of material is comprised of polysilicon or amorphous silicon and said second sacrificial material is comprised of OPL.
7. A method of forming a FinFET transistor above an active region defined in a semiconductor substrate, comprising:
forming a plurality of fins in said semiconductor substrate;
forming a sacrificial gate structure above said plurality of fins;
performing an epitaxial deposition fin-merger process to form a plurality of merged-fin regions from portions of said plurality of fins that define a plurality of source/drain regions for said transistor;
removing said sacrificial gate structure and forming a replacement gate structure in its place;
at some point after forming said replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of said plurality of source/drain regions;
with said replacement gate structure in position, forming a first sacrificial layer of material above said source/drain regions;
patterning said first sacrificial layer of material to define features in said patterned first sacrificial layer of material;
forming a layer of insulating material around said patterned first sacrificial layer of material;
removing remaining portions of said first sacrificial layer of material so as to define a plurality of source/drain contact openings in said layer of insulating material;
forming a second sacrificial material in said source/drain contact openings;
masking said second sacrificial material;
with said second sacrificial material masked, forming a gate contact opening in said layer of insulating material to expose a portion of said replacement gate structure;
removing said second sacrificial material from within said source/drain contact openings so as to thereby expose said metal silicide layer; and
after removing said second sacrificial material from within said source/drain contact openings, performing a plurality of common process operations to form at least one source/drain contact structure in said source/drain contact openings and a gate contact structure in said gate contact opening at the same time.
8. The method of claim 7 , wherein said at least one source/drain contact structure is formed such that it is conductively coupled to a portion of said metal silicide layer and a dimension of said at least one source/drain contact structure in a gate width direction of said transistor is less than a dimension of said source/drain region in said gate width direction.