Granted Patent B2

US 9,383,807 · App. 14/043,445 · Granted Jul 5, 2016

Abstract

Claims (55)

1. A microcontroller system comprising:

a processor;

a plurality of modules organized into a plurality of power domains; and

a power manager coupled to each of the power domains, wherein the power manager is configured to, while the processor is inactive, manage the power mode of each power domain by:

placing the power domain into a first power mode if the microcontroller system has asserted a power trigger for any module in the power domain or if any module in the power domain has asserted a power keeper, wherein a power trigger is a trigger for a module in the power domain to perform a task, and wherein a power keeper is an indication to keep the power domain the first power mode; and

placing the power domain into a second power mode that uses less power than the first power mode if the microcontroller system is not asserting a power trigger for any module in the power domain and no module in the power domain has asserted a power keeper,

wherein a first module of the plurality of modules is configured to assert a power trigger to a second module of the plurality of modules using an event coordinator module coupled to each of the first and second modules and the power manager, the event coordinator module being configured to route power triggers between the modules.

2. The microcontroller system of claim 1 , wherein a third module of the plurality of modules is configured to assert a power keeper by asserting a clock request to provide a clock signal to perform a first task.

3. The microcontroller system of claim 1 , wherein a third module of the plurality of modules in a first power domain is configured to:

while the first power domain is in the second power mode, receive a first trigger to perform a first task;

after the power manager puts the first power domain into the first power mode, assert a clock request, thereby asserting a power keeper on the power manager for the first domain;

acknowledge the first trigger;

perform the first task; and

after performing the first task, relinquish the clock request so that the power manager can put the first power domain back into the second power mode.

4. The microcontroller system of claim 1 , wherein the first module of the plurality of modules is in a first power domain and configured to:

while the first power domain is in the second power mode, receive a first trigger to perform a first task;

after the power manager puts the first power domain into the first power mode, assert a clock request, thereby asserting a power keeper on the power manager for the first power domain;

acknowledge the first trigger;

perform the first task and assert a second trigger on the second module in a second power domain, thereby asserting the power trigger on the power manager for the second bower domain; and

after performing the first task and receiving an acknowledgement for the second trigger, relinquish the clock request so that the power manager can put the first power domain back into the second power mode.

5. The microcontroller system of claim 1 , wherein the first power mode is an active mode where the modules of a power domain can perform a first plurality of tasks, and wherein the second power mode is a retention mode where the modules of a power domain cannot perform a second plurality of tasks and the modules can retain state information.

6. A microcontroller system organized into a plurality of power domains, the microcontroller system comprising:

a processor;

a clock controller configured to provide a clock signal to a plurality of modules;

an event controller configured to route trigger events between the modules; and

a power manager configured to, while the processor is inactive, toggle a first power domain between an active power mode and a retention power mode based on whether the clock controller is indicating any clock requests from the first power domain and whether the event controller is indicating any trigger events to the first power domain,

wherein the event controller is coupled to first and second modules of the plurality of modules and the power manager, and configured to route a trigger event asserted by the first module to the second module.

7. The microcontroller system of claim 6 , wherein the power manager is configured to toggle the first power domain from the retention power mode to the active power mode in response to receiving a first event indication from the event controller that a trigger event has been asserted on the first power domain.

8. The microcontroller system of claim 7 , wherein the power manager is configured to toggle the first power domain from the active power mode to the retention power mode in response to receiving a second event indication from the event controller that the trigger event has been acknowledged and receiving a clock indication from the clock controller that the first power domain has relinquished an asserted clock request.

9. The microcontroller system of claim 6 , further comprising a real time counter (RTC), an analog-to-digital converter (ADC), and a direct memory access module (DMA); wherein the ADC and the event controller are in the first power domain and the DMA is in a second power domain; and wherein the power manager is configured to:

toggle the first power domain from the retention power mode to the active power mode in response to an RTC event trigger from the RTC, so that the event controller asserts an event clock request on the clock controller and routes the RTC event trigger to the ADC, and then the ADC asserts an ADC clock request on the clock controller and performs a task and asserts an ADC event trigger on the DMA;

toggle the second power domain from the retention power mode to the active power mode in response to the ADC event trigger, so that the DMA asserts a DMA clock request on the clock controller and executes a transfer from the ADC to a memory, and then the DMA acknowledges the ADC event trigger; and

toggle the first and second power domains from the active power mode to the retention power mode in response to the ADC acknowledging the RTC event trigger, the DMA acknowledging the ADC event trigger, and the event controller relinquishing the event clock request, the ADC relinquishing the ADC clock request, and the DMA relinquishing the DMA clock request.

10. The microcontroller system of claim 6 , further comprising a real time counter (RTC), an analog-to-digital converter (ADC), and a direct memory access module (DMA); wherein the ADC and the event controller are in the first power domain and the DMA is in a second power domain and the processor is in a third power domain; and wherein the power manager is configured to:

toggle the first power domain from the retention power mode to the active power mode in response to an RTC event trigger from the RTC, so that the event controller asserts an event clock request on the clock controller and routes the RTC event trigger to the ADC, and then the ADC asserts an ADC clock request on the clock controller and performs a task and asserts an ADC event trigger on the DMA;

toggle the second power domain from the retention power mode to the active power mode in response to the ADC event trigger, so that the DMA asserts a DMA clock request on the clock controller and executes a transfer from the ADC to a memory, and then the DMA asserts an interrupt; and

toggle the third power domain from the retention power mode to the active power mode so that the processor can handle the interrupt.

11. A method performed by a power manager of a microcontroller system comprising a processor and a plurality of modules organized into a plurality of power domains, the method comprising, for each power domain:

while the processor is inactive, placing the power domain into a first power mode if the microcontroller system has asserted a power trigger for any module in the power domain or if any module in the power domain has asserted a power keeper, wherein a power trigger is a trigger for a module in the power domain to perform a task, and wherein a power keeper is an indication to keep the power domain the first power mode; and

placing the power domain into a second power mode that uses less power than the first power mode if the microcontroller system is not asserting a power trigger for any module in the power domain and no module in the power domain has asserted a power keeper,

wherein a first module of the plurality of modules is configured to assert a power trigger to a second module of the plurality of modules using an event coordinator module coupled to each of the first and second modules and the power manager, the event coordinator module being configured to route power triggers between the modules.

12. The method of claim 11 , wherein a third module of the plurality of modules is configured to assert a power keeper by asserting a clock request to provide a clock signal to perform a first task.

13. The method of claim 11 , wherein a third module of the plurality of modules in a first power domain is configured to:

while the first power domain is in the second power mode, receive a first trigger to perform a first task;

after the power manager puts the first power domain into the first power mode, assert a clock request, thereby asserting a power keeper on the power manager for the first domain;

acknowledge the first trigger;

perform the first task; and

after performing the first task, relinquish the clock request so that the power manager can put the first power domain back into the second power mode.

14. The method of claim 11 , wherein the first module of the plurality of modules is in a first power domain and configured to:

while the first power domain is in the second power mode, receive a first trigger to perform a first task;

after the power manager puts the first power domain into the first power mode, assert a clock request, thereby asserting a power keeper on the power manager for the first power domain;

acknowledge the first trigger;

perform the first task and assert a second trigger on the second module in a second power domain, thereby asserting the power trigger on the power manager for the second domain; and

after performing the first task and receiving an acknowledgement for the second trigger, relinquish the clock request so that the power manager can put the first power domain back into the second power mode.

15. The method of claim 11 , wherein the first power mode is an active mode where the modules of a power domain can perform a first plurality of tasks, and wherein the second power mode is a retention mode where the modules of a power domain cannot perform a second plurality of tasks and the modules can retain state information.

Assignments (18)