Temperature compensation of conductive bridge memory arrays
Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.
1. A method for operating a memory array, comprising:
acquiring a temperature associated with the memory array, the memory array comprises a cross-point memory array and includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction perpendicular to the first direction, the plurality of word lines includes a selected word line and a plurality of unselected word lines, the plurality of bit lines includes a selected bit line and a plurality of unselected bit lines, the memory array includes a first storage element disposed between the selected word line and the selected bit line, the memory array includes a plurality of unselected storage elements disposed between the plurality of unselected word lines and the plurality of unselected bit lines;
applying a first voltage difference across the plurality of unselected storage elements based on the temperature; and
setting the first storage element into a first state while performing the applying a first voltage difference across the plurality of unselected storage elements, the setting the first storage element into a first state includes applying a second voltage difference across the first storage element.
2. The method of claim 1 , wherein:
the applying a first voltage difference across the plurality of unselected storage elements includes applying one or more unselected word line voltages to the plurality of unselected word lines and applying one or more unselected bit line voltages to the plurality of unselected bit lines; and
the applying a second voltage difference across the first storage element includes applying a selected word line voltage to the selected word line and applying a selected bit line voltage to the selected bit line.
3. The method of claim 1 , wherein:
the first state is associated with a programming state of the first storage element; and
the second voltage difference across the first storage element is associated with a programming voltage of the first storage element.
4. The method of claim 1 , wherein:
the first state is associated with a reading state of the first storage element; and
the second voltage difference across the first storage element is associated with a reading voltage of the first storage element.
5. The method of claim 2 , further comprising:
sensing the first storage element while applying the second voltage difference across the first storage element.
6. The method of claim 2 , wherein:
the applying one or more unselected word line voltages to the plurality of unselected word lines includes generating the one or more unselected word line voltages based on the temperature.
7. The method of claim 2 , further comprising:
determining a particular number of write cycles associated with the memory array, the applying one or more unselected word line voltages to the plurality of unselected word lines includes generating the one or more unselected word line voltages based on the temperature and the particular number of write cycles.
8. The method of claim 7 , wherein:
the determining a particular number of write cycles includes determining a number of write cycles that have occurred since a last erase of the memory array.
9. The method of claim 2 , further comprising:
determining a particular number of write cycles associated with a page within the memory array, the page is associated with the selected word line, the applying one or more unselected word line voltages to the plurality of unselected word lines includes generating the one or more unselected word line voltages based on the temperature and the particular number of write cycles.
10. The method of claim 9 , wherein:
the determining a particular number of write cycles includes determining a number of write cycles that have occurred since a last refresh of the page.
11. The method of claim 2 , further comprising:
determining a memory layer associated with the first storage element, the applying one or more unselected word line voltages to the plurality of unselected word lines includes generating the one or more unselected word line voltages based on the temperature and the memory layer associated with the first storage element.
12. The method of claim 1 , wherein:
the plurality of bit lines comprises vertically oriented bit lines.
13. The method of claim 1 , wherein:
the first storage element comprises a non-volatile storage element.
14. The method of claim 1 , wherein:
the acquiring a temperature associated with the memory array includes sensing the temperature using a temperature sensor.
15. A method for operating a memory array, comprising:
detecting a first condition associated with the memory array, the detecting a first condition includes at least one of detecting a temperature associated with the memory array or detecting a particular number of write cycles associated with the memory array, the memory array comprises a cross-point memory array and includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a selected word line and a plurality of unselected word lines, the plurality of bit lines includes a selected bit line and a plurality of unselected bit lines, the memory array includes a first storage element disposed between the selected word line and the selected bit line, the memory array includes a plurality of unselected storage elements disposed between the plurality of unselected word lines and the plurality of unselected bit lines;
applying a first voltage difference across the plurality of unselected storage elements based on the first condition;
applying a second voltage difference across the first storage element while applying the first voltage difference across the plurality of unselected storage elements; and
sensing the first storage element while applying the second voltage difference across the first storage element.
16. The method of claim 15 , wherein:
the applying a first voltage difference across the plurality of unselected storage elements includes applying one or more unselected word line voltages to the plurality of unselected word lines and applying one or more unselected bit line voltages to the plurality of unselected bit lines; and
the applying a second voltage difference across the first storage element includes applying a selected word line voltage to the selected word line and applying a selected bit line voltage to the selected bit line.
17. The method of claim 16 , wherein:
the applying one or more unselected word line voltages to the plurality of unselected word lines includes generating the one or more unselected word line voltages based on the temperature.
18. The method of claim 16 , further comprising:
determining the particular number of write cycles associated with the memory array based on a number of write cycles that have occurred since a last erase of the memory array, the applying one or more unselected word line voltages to the plurality of unselected word lines includes generating the one or more unselected word line voltages based on the temperature and the particular number of write cycles.
19. A non-volatile storage system, comprising:
a memory array, the memory array comprises a cross-point memory array and includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a selected word line and a plurality of unselected word lines, the plurality of bit lines includes a selected bit line and a plurality of unselected bit lines, the memory array includes a first storage element disposed between the selected word line and the selected bit line, the memory array includes a plurality of unselected storage elements disposed between the plurality of unselected word lines and the plurality of unselected bit lines; and
one or more managing circuits in communication with the plurality of word lines and the plurality of bit lines, the one or more managing circuits acquire a temperature associated with the memory array, the one or more managing circuits cause a first voltage difference to be applied across the plurality of unselected storage elements based on the temperature, the one or more managing circuits cause a second voltage difference to be applied across the first storage element while the first voltage difference is applied across the plurality of unselected storage elements, the one or more managing circuits cause the first storage element to be sensed while the second voltage difference is applied across the first storage element.
20. The non-volatile storage system of claim 19 , wherein:
the first voltage difference is applied across the plurality of unselected storage elements by applying one or more unselected word line voltages to the plurality of unselected word lines and applying one or more unselected bit line voltages to the plurality of unselected bit lines; and
the second voltage difference is applied across the first storage element by applying a selected word line voltage to the selected word line and applying a selected bit line voltage to the selected bit line.
21. The non-volatile storage system of claim 20 , wherein:
the one or more managing circuits determine a particular number of write cycles associated with the memory array based on a number of write cycles that have occurred since a last erase of the memory array, the one or more managing circuits cause the first voltage difference to be applied across the plurality of unselected storage elements based on the temperature and the particular number of write cycles.
22. The non-volatile storage system of claim 20 , wherein:
the one or more managing circuits determine a particular number of write cycles associated with a page within the memory array, the page is associated with the selected word line, the one or more managing circuits cause the first voltage difference to be applied across the plurality of unselected storage elements based on the temperature and the particular number of write cycles.
23. The non-volatile storage system of claim 20 , wherein:
the one or more managing circuits determine a memory layer associated with the first storage element, the one or more managing circuits cause the first voltage difference to be applied across the plurality of unselected storage elements based on the temperature and the memory layer associated with the first storage element.
24. The non-volatile storage system of claim 19 , wherein:
the one or more managing circuits cause the first storage element to be sensed during a read operation of the first storage element; and
the first storage element comprises a non-volatile storage element.
25. The non-volatile storage system of claim 19 , further comprising:
a temperature sensor, the temperature sensor determines the temperature associated with the memory array.