Granted Patent B2

US 9,975,145 · App. 14/045,689 · Granted May 22, 2018

Abstract

Claims (34)

1. An electrical waveform generating circuit comprising:

a pair of Pulse Amplitude Controlled Switching Current Sources (PACS);

a gate pulse driver circuit coupled to an input of each of the pair of PACS for sending gate pulses for driving the pair of PACS;

a digital-to-analog converter (DAC) circuit coupled to the gate pulse driver circuit for controlling amplitudes of the gate pulses; and

a transducer coupled to the PACS;

wherein the gate pulse driver circuit is configured to receive timing control signals that correspond to a weighting of the PACS.

2. The electrical waveform generating circuit of claim 1 , further comprising a pair of amplifiers, wherein each amplifier is coupled to one of the PACS.

3. The electrical waveform generating circuit of claim 2 , wherein the pair of amplifiers, are common gate amplifiers.

4. The electrical waveform generating circuit of claim 2 , wherein the pair of amplifiers, comprises a P-MOSFET amplifier and an N-MOSFET amplifier, wherein the gate terminals of the P-MOSFET amplifier and an N-MOSFET amplifier are coupled to voltage supplies.

5. The electrical waveform generating circuit of claim 4 , further comprising a pair of back-to-back coupled MOSFETs coupled to drain terminals of the P-MOSFET amplifier and an N-MOSFET amplifier.

6. The electrical waveform generating circuit of claim 5 , further comprising a bleed resistor coupled to the back-to-back coupled MOSFETs.

7. The electrical waveform generating circuit of claim 1 , further comprising a pair of cross coupled diodes coupled to the transducer.

8. An electrical waveform generating circuit comprising:

a programmable switch current source-driver;

a plurality of Pulse Voltage Amplitude Controlled Switching Current Source (PACS) configured into a high voltage complementary P- and N-type MOSFETs formed common-gate power amplifier;

a pair of complementary digital programmable voltage amplitude gate-driver capacitive circuits coupled to inputs of the PACS for controlling the output current waveforms and timing; and

a transducer coupled to drains of the complementary P- and N-type MOSFETs.

9. The electrical waveform generating circuit in accordance with claim 8 , wherein the programmable current source-driver comprises:

a pair of pulse voltage amplitude control switching current source drivers; and

a low reference voltage power supply connected to each pulse voltage amplitude control switching current source driver as a bias voltage.

10. The electrical waveform generating circuit in accordance with claim 8 wherein the pair of complementary digital programmable voltage amplitude gate-driver capacitive circuits comprises:

a pair of positive and negative high voltage isolation-barriers for at least one of unidirectional and bidirectional control signals from at least one of to and from a digital circuit reference to ground; and

differential high voltage AC signals supplied through a pair of capacitors, the capacitors coupled to the PACS.

11. The electrical waveform generating circuit in accordance with claim 8 , further comprising a pair of digital to analog converters, wherein one of the pair of digital to analog converters is coupled to each of the pair of complementary digital programmable voltage amplitude gate-driver capacitive circuits.

12. The electrical waveform generating circuit in accordance with claim 11 , wherein the digital to analog converters control a pulse voltage amplitude, and further control an output current level of the PACS.

13. An electrical waveform generating circuit comprising:

a pulse voltage amplitude control switching current source circuit;

a pair of switching control circuits coupled to a floating source-driver and control circuit;

a plurality of complementary P- and N-type MOSFETs coupled to the pair of switching control circuits; and

a transducer coupled to the complementary P- and N-type MOSFETs.

14. An electrical waveform generating circuit in accordance with claim 13 , wherein the plurality of complementary P- and N-type MOSFETs coupled to the switching control circuits comprises:

a P-type higher voltage, common gate MOSFET output circuits coupled to the pulse amplitude controlled switching current source circuit; and

a N-type higher voltage, common gate MOSFET output circuits coupled to the pulse amplitude controlled switching current source circuit;

wherein a drain terminal of each of the pair of P-type MOSFET is coupled to a drain terminal of each of the pair of P-type MOSFET.

Assignments (17)