Method of fabricating a self-aligning damascene memory structure
View Patent ↗A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
1. A method of forming a memory cell, the method comprising:
forming a first opening self-aligned with a first pillar-shaped element that comprises a first semiconductor material; and
depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element.
2. The method of claim 1 , wherein the first semiconductor material comprises N-type semiconductor material, and the second semiconductor material comprises P-type semiconductor material.
3. The method of claim 1 , wherein the first semiconductor material comprises P-type semiconductor material, and the second semiconductor material comprises N-type semiconductor material.
4. The method of claim 1 , further comprising forming a second opening self-aligned with the second pillar shaped element.
5. The method of claim 4 , further comprising filling the second opening with conductive material to form a conductor.
6. The method of claim 4 , further comprising filling the second opening with a third semiconductor material.
7. The method of claim 6 , wherein the first semiconductor material comprises a heavily-doped N-type semiconductor material, the second semiconductor material comprises a lightly-doped N-type semiconductor material and the third semiconductor material comprises a heavily doped P-type semiconductor material.
8. The method of claim 6 , wherein the first semiconductor material comprises a heavily-doped P-type semiconductor material, the second semiconductor material comprises a lightly-doped N-type semiconductor material and the third semiconductor material comprises a heavily doped N-type semiconductor material.
9. A memory cell formed according to the method of claim 1 .
10. A three-dimensional array of memory cells formed according to the method of claim 1 .
11. A method of forming a memory cell, the method comprising:
depositing a sacrificial material over a first semiconductor material;
patterning and etching the sacrificial material to form first pillar shaped elements;
depositing an insulating material between the first pillar shaped elements;
removing the sacrificial material to form a mold having open areas between the insulating material; and
depositing a second semiconductor material or a conductive material in the open areas.
12. The method of claim 11 , further comprising after the removing of the sacrificial material:
doping a portion of the first semiconductor material to form a highly doped region.
13. The method of claim 11 , wherein the sacrificial material comprises a dielectric material.
14. The method of claim 11 , wherein the sacrificial material comprises Si3N4.
15. The method of claim 11 , wherein the insulating material comprises one or more of silicon oxide, silicon dioxide, silicon oxynitride, or a high density plasma oxide.
16. The method of claim 11 , wherein the first semiconductor material comprises a heavily-doped N-type semiconductor material and the second semiconductor material comprises a lightly-doped N-type semiconductor material.
17. The method of claim 11 , wherein the first semiconductor material comprises a heavily doped P-type semiconductor material.
18. A memory cell formed according to the method of claim 11 .
19. A three-dimensional array of memory cells formed according to the method of claim 11 .
20. A method of forming a memory cell, the method comprising:
depositing a first sacrificial material over a first semiconductor material;
patterning and etching the first sacrificial material to form first pillar shaped elements;
depositing a first insulating material between the first pillar shaped elements;
removing the first sacrificial material to form a first mold having first open areas between the first insulating material;
depositing a second semiconductor material in the first open areas;
depositing a second sacrificial material over the second semiconductor material;
patterning and etching the second sacrificial material to form second pillar shaped elements;
depositing a second insulating material between the second pillar shaped elements;
removing the second sacrificial material to form a second mold having second open areas between the second insulating material;
doping a portion of the second semiconductor material to form a third semiconductor layer; and
depositing a conductive material in the second open areas.