Granted Patent B2

US 9,153,568 · App. 14/156,729 · Granted Oct 6, 2015

Abstract

Claims (35)

1. An electrostatic discharge protection device, comprising:

an N well;

a P type doping region, disposed in the N well;

a first N type doping region, disposed in the P type doping region;

a plurality of N type sub-doping regions, disposed in the P type doping region in parallel, wherein the N type sub-doping regions do not contact to the first N type doping region, and the N type sub-doping regions are electrically connected to a first source rail-line;

a first N+ type doping region, disposed in the first N type doping region;

a first P+ type doping region, disposed in the first N doping region, wherein the first N+ doping region and the first P+ doping region are electrically connected to a pad;

a second N+ doping region, disposed in the P type doping region, wherein second P+ type doping region and the second N+ doping region are electrically connected to a second source rail-line;

wherein the N type sub-doping regions are disposed between the first N type doping region and the second N+ doping region;

wherein when the first source rail-line is electrically connected to a system voltage and the second source rail-line is electrically connected to a ground voltage, there is a depletion region generated between the N type sub-doping region and the P type doping region so as to block a channel current between the first N+ type doping region and the second N+ type doping region.

2. The electrostatic discharge protection device according to claim 1 , wherein the electrostatic discharge protection device is a silicon-controlled rectifier, and the N well is disposed in a substrate, and doping concentration of the N well is lower than doping concentration of the first N type doping region.

3. The electrostatic discharge protection device according to claim 2 , wherein when the first source rail-line is electrically connected to a system voltage and the second source rail-line is electrically connected to a ground voltage, a holding voltage and a trigger voltage both increase and holding voltage is larger than the system voltage.

4. The electrostatic discharge protection device according to claim 1 , wherein the P type doping region is P type graded region.

5. The electrostatic discharge protection device according to claim 1 , wherein the first N type doping region is N type graded region and the N type sub-doping regions are N type graded region.

6. A chip, comprising:

a core circuit;

a first source rail-line;

a second source rail-line; and

a plurality of pad units, surrounding the core circuit, each of the plurality of pad units comprising:

a pad, electrically connected to the pad circuit; and

an electrostatic discharge protection device according to claim 1 , disposed next to the pad and electrically connected to the first source rail-line and the second source rail-line, wherein the electrostatic discharge protection device of each of the plurality of pad units is disposed between the first source rail-line and the second source rail-line;

wherein when the first source rail-line is electrically connected to a system voltage and the second source rail-line is electrically connected to a ground voltage, there is a depletion region generated between the N type sub-doping region and the P type doping region so as to block a channel current between the first N+ type doping region and the second N+ type doping region.

7. A manufacturing method for an electrostatic discharge protection device, comprising:

providing a substrate;

forming a N well in the substrate;

forming a P type doping region in the N well;

forming a first N type doping region in the P type doping region;

forming a plurality of N type sub-doping regions in parallel in the P type doping region, wherein the N type sub-doping regions do not contact to the first N type doping region, and the N type sub-doping regions are electrically connected to a first source rail-line;

forming a first N+ type doping region in the first N type doping region;

forming a first P+ doping region in the first N type doping region, and the first P+ doping region is connected next to the first N+ type doping region, wherein the first N+ type doping region and the first P+ doping region are electrically connected to a pad;

forming a second N+ type doping region in the P type doping region; and

forming a second P+ doping region in the P type doping region and the second P+ doping region connected next to the second N+ type doping region, wherein the second P+ doping region and the second N+ type doping region are connected to a second source rail-line, and when the first source rail-line is electrically connected to a system voltage and the second source rail-line is electrically connected to a ground voltage, there is a depletion region generated between the N type sub-doping region and the P type doping region so as to block a channel current between the first N+ type doping region and the second N+ type doping region.

8. The manufacturing method for an electrostatic discharge protection device according to claim 7 , wherein the N type sub-doping regions are disposed between the first N type doping region and the second N+ type doping region.

9. The manufacturing method for an electrostatic discharge protection device according to claim 7 , wherein the electrostatic discharge protection device is a silicon-controlled rectifier and the N well is disposed in a substrate.

10. The manufacturing method for an electrostatic discharge protection device according to claim 7 , wherein when the first source rail-line is electrically connected to a system voltage and the second source rail-line is electrically connected to a ground voltage, a holding voltage and a trigger voltage both increase and holding voltage is larger than the system voltage.

Assignments (17)