Stacked semiconductor device
A stacked semiconductor device includes a first pair of vertically stacked self-aligned nanowires, a second pair of vertically stacked self-aligned nanowires, and a gate upon a semiconductor substrate, the gate surrounding portions of the first pair of vertically stacked self-aligned nanowires and the second pair of vertically stacked self-aligned nanowires. First epitaxy may merge the first pair of vertically stacked self-aligned nanowires and second epitaxy may merge second pair of vertically stacked self-aligned nanowires. The stacked semiconductor device may be fabricated by forming a lattice-fin upon the semiconductor substrate and the gate surrounding a portion of the lattice-fin. The vertically stacked self-aligned nanowires may be formed by selectively removing a plurality of layers from the lattice-fin.
1. A stacked semiconductor device fabrication process comprising:
forming a lattice-fin upon a semiconductor substrate;
forming a gate upon the semiconductor substrate surrounding a portion of the lattice-fin;
forming vertically stacked self-aligned nanowires by selectively removing a plurality of layers from the lattice fin;
forming first epitaxy upon sidewalls of a plurality of vertically stacked self-aligned nanowires in a first nanowire group, the first epitaxy merging the first nanowire group in source and drain regions of the stacked semiconductor device, and;
forming second epitaxy upon sidewalls of a plurality of nanowires in a second nanowire group, the second epitaxy merging the plurality of nanowires in the second nanowire group in source and drain regions of the stacked semiconductor device.
2. The semiconductor device fabrication process of claim 1 , further comprising:
forming a super-lattice upon the semiconductor substrate, the super-lattice comprising a first layered lattice formed upon the semiconductor substrate, an inter-lattice material formed upon the first layered lattice, and a second layered lattice formed upon the inter-lattice material.
3. The semiconductor device fabrication process of claim 2 , wherein the first layered lattice comprises alternating first semiconductor layers and second semiconductor layers and wherein the second layered lattice comprises oppositely orientated alternating first semiconductor layers and second semiconductor layers.
4. The semiconductor device fabrication process of claim 3 , wherein the lattice-fin is formed from the super-lattice and wherein the stacked self aligned nanowires are formed by removing the first semiconductor layers.
5. The semiconductor device fabrication process of claim 3 , wherein the lattice-fin is formed from the super-lattice and wherein the stacked self aligned nanowires are formed by removing the second semiconductor layers.
6. The semiconductor device fabrication process of claim 1 , wherein the merged first nanowire group forms a first field effect transistor (FET) structure of opposite polarity relative to a second FET structure formed from the merged second nanowire group.
7. The semiconductor device fabrication process of claim 1 , wherein the gate is a dummy gate structure.