ADC sequencing
View Patent ↗A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.
1. A device comprising:
a memory configured to store memory descriptors;
a peripheral controller configured to manage a peripheral module; and
a direct memory access system (DMA system) configured to autonomously sequence operations performed by the peripheral module by performing operations comprising:
accessing, without a central processing unit (CPU) intervention, a memory descriptor stored in the memory, wherein the memory descriptor includes information associated with a second operation to be performed by the peripheral module;
receiving, from the peripheral controller, a ready signal indicating that a first operation performed by the peripheral module is completed; and
in response to receiving the ready signal, transferring, from the memory to the peripheral controller without CPU intervention, the memory descriptor that includes information associated with the second operation to be performed by the peripheral module,
wherein the peripheral controller is configured to set parameters for operations performed by the peripheral module based on information included in one or more memory descriptors received from the DMA system, and wherein the information included in the one or more memory descriptors are stored in a first register associated with the peripheral controller that is configured to store information about operations to be performed by the peripheral module.
2. The device of claim 1 , further comprising a CPU that is coupled to at least one of the memory, the DMA system or the peripheral controller, wherein the CPU is configured to be idle or performing reduced activities at a time when operations are performed by the peripheral module.
3. The device of claim 2 , wherein the CPU implements a reduced instruction set computer (RISC) instruction set architecture (ISA).
4. The device of claim 1 , further comprising a CPU that is coupled to at least one of the memory, the DMA system or the peripheral controller, wherein the CPU is configured to be performing activities unrelated to the peripheral module at a time when operations are performed by the peripheral module.
5. The device of claim 1 , wherein the memory descriptors in the memory are managed by the DMA system, and
wherein the peripheral controller is not directly coupled to the memory.
6. The device of claim 1 , wherein the peripheral controller includes one or more registers that are configured to store one of settings, data or results for the operations performed by the peripheral module, and wherein the peripheral controller is configured to:
receive a memory descriptor from the DMA system via a peripheral data bus;
extract, from the memory descriptor, information about an operation to be performed by the peripheral module; and
store the information extracted from the memory descriptor in the first register.
7. The device of claim 6 , wherein the peripheral controller is further configured to:
store a result of an operation performed by the peripheral module in a second register associated with the peripheral controller; and
generate the ready signal indicating that the operation performed by the peripheral module is completed.
8. The device of claim 7 , wherein the result of the operation performed by the peripheral module is transferred from the second register to the memory using a memory descriptor, and wherein the DMA system is configured to:
receive, from the peripheral controller, the ready signal indicating that the operation performed by the peripheral module is completed; and
in response to receiving the ready signal, transfer the result of the operation from the second register to the memory using the memory descriptor.
9. The device of claim 1 , wherein the ready signal is associated with a single transfer cycle of memory descriptors.
10. The device of claim 1 , wherein a memory descriptor transferred from the memory to the peripheral controller include per-channel settings for the next operation to be performed by the peripheral module.
11. The device of claim 1 , wherein the information included in a memory descriptor are arranged as bit fields that correspond to bit fields in the first register associated with the peripheral controller.
12. The device of claim 1 , wherein a number of the operations performed by the peripheral module is limited by a number of the memory descriptors stored in the memory.
13. The device of claim 1 , wherein an order of the operations performed by the peripheral module is based on an arrangement of the memory descriptors in the memory.
14. The device of claim 1 , wherein the memory includes one of a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or an EEPROM.
15. The device of claim 1 , wherein the peripheral module includes an analog-to-digital converter (ADC), and wherein the peripheral controller includes an ADC controller.
16. The device of claim 1 , wherein a size of a memory descriptor is one of 32 bit, 64 bit or 128 bit.
17. The device of claim 1 , wherein a memory descriptor is configured to store a set of parameters associated with a DMA transfer sequence.
18. The device of claim 1 , wherein a memory descriptor comprises a structure in memory that includes a configuration word.
19. A method comprising:
accessing, by a direct memory access (DMA) system, a memory descriptor stored in a memory, wherein the memory descriptor includes information associated with a second operation to be performed by a peripheral module, and wherein the accessing is performed by the DMA without CPU intervention;
receiving, at the DMA system, a ready signal from a peripheral controller that is configured to manage the peripheral module, wherein the ready signal indicates that a first operation performed by the peripheral module is completed; and
in response to receiving the ready signal, transferring, by the DMA system, from the memory to the peripheral controller without CPU intervention, the memory descriptor that includes information associated with the second operation to be performed by the peripheral module,
wherein the information included in the memory descriptor is stored in a first register associated with the peripheral controller that is configured to store information about operations to be performed by the peripheral module.
20. The method of claim 19 , wherein a result of the first operation is stored in a second register associated with the peripheral controller, the method further comprising:
in response to receiving the ready signal, transferring, by the DMA system, a result of the first operation from the second register associated with the controller to the memory using another memory descriptor that is associated with the first operation, wherein the transferring is performed by the DMA without CPU intervention.