Methods of forming printable integrated circuit devices and devices formed thereby

1. A method of forming an integrated circuit device, comprising:

forming a sacrificial layer on a handling substrate;

forming a semiconductor active layer on the sacrificial layer;

selectively etching through the semiconductor active layer and the sacrificial layer to define a patterned substrate comprising a first portion of the semiconductor active layer;

forming a multi-layer electrical interconnect network on the patterned substrate;

encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer;

selectively etching through the inorganic capping layer and the first portion of the semiconductor active layer to expose the sacrificial layer; and

selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the inorganic capping layer.

2. The method of claim 1 , wherein said encapsulating is preceded by roughening the upper surface of the first portion of the semiconductor active layer.

3. The method of claim 2 , wherein said roughening the upper surface of the first portion of the semiconductor active layer comprises exposing the upper surface to a plasma etchant.

4. The method of claim 1 , wherein said selectively etching through the semiconductor active layer and the sacrificial layer comprises selectively etching the semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom that exposes the handling substrate; and wherein forming a multi-layer electrical interconnect network is preceded by filling the trench with an inorganic anchor.

5. The method of claim 4 , wherein selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate comprises exposing a sidewall of the inorganic anchor.

6. The method of claim 4 , wherein the trench is a ring-shaped trench that surrounds the patterned substrate.

7. The method of claim 4 , wherein filling the trench with an inorganic anchor comprises depositing a semiconductor layer into the trench and onto the patterned substrate and then planarizing the deposited semiconductor layer to define a semiconductor anchor.

8. The method of claim 4 , wherein the multi-layer electrical interconnect network comprises a plurality of interlayer dielectric layers; and wherein said encapsulating is preceded by a step of selectively etching through the plurality of interlayer dielectric layers to expose the inorganic anchor.

9. The method of claim 8 , wherein said encapsulating comprises depositing the inorganic capping layer onto the exposed inorganic anchor.

10. The method of claim 8 , wherein the inorganic capping layer comprises amorphous silicon and the inorganic anchor comprises polysilicon.

11. The method of claim 3 , wherein said selectively etching through the semiconductor active layer and the sacrificial layer comprises selectively etching the semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom that exposes the handling substrate; and wherein forming a multi-layer electrical interconnect network is preceded by filling the trench with an inorganic anchor.

12. The method of claim 11 , wherein selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate comprises exposing a sidewall of the inorganic anchor.

13. The method of claim 11 , wherein the trench is a rectangular ring-shaped trench that surrounds the patterned substrate.

14. The method of claim 11 , wherein filling the trench with an inorganic anchor comprises depositing a polysilicon layer into the trench and onto the patterned substrate and then removing excess portions of the deposited polysilicon layer using a planarization technique to define a semiconductor anchor.

15. The method of claim 11 , wherein the multi-layer electrical interconnect network comprises a plurality of interlayer dielectric layers; and wherein said encapsulating is preceded by a step of selectively etching through the plurality of interlayer dielectric layers to expose the inorganic anchor.

16. The method of claim 15 , wherein said encapsulating comprises depositing an amorphous silicon capping layer onto the exposed inorganic anchor.

17. The method of claim 1 , wherein said selectively etching through the semiconductor active layer and the sacrificial layer comprises selectively etching the semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom that exposes the handling substrate; and wherein forming a multi-layer electrical interconnect network is preceded by filling the trench with an inorganic anchor.

18. The method of claim 17 , wherein selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate comprises exposing a sidewall of the inorganic anchor.