High stack 3D memory and method of making

1. A method of making a monolithic three dimensional NAND device, comprising:

forming a stack of alternating layers of a first material and a second material different from the first material over a substrate;

forming a mask layer over the stack;

patterning the mask layer to form at least on opening in the mask layer to expose a top layer of the stack;

forming a metal block in the at least one opening in the mask layer;

etching the stack by metal induced localized etch using the metal block in the at least one opening in the mask layer to form at least one opening in the stack; and

forming at least one layer of the NAND device in the at least one opening.

2. The method of claim 1 , further comprising removing the metal block from a bottom of the at least one opening in the stack and removing the mask layer from the stack prior to the step of forming at least one layer of the NAND device.

3. The method of claim 1 , wherein the first material comprises doped polysilicon and the second material comprises intrinsic polysilicon.

4. The method of claim 3 , wherein:

the step of etching the stack comprises providing a solution comprising hydrogen peroxide and hydrofluoric acid to the metal block in the at least one opening in the mask layer;

the hydrogen peroxide oxidizes a surface of the doped or intrinsic polysilicon layer below the metal block to form a silicon oxide region below the metal block;

the hydrofluoric acid etches the silicon oxide region causing the metal block to sink into the stack; and

the silicon oxide region formation, silicon oxide region etching and metal block sinking into the stack are repeated a plurality of times to form the opening.

5. The method of claim 1 , wherein the at least one opening has substantially vertical sidewalls and a substantially uniform cross section when viewed from the top.

6. The method of claim 5 , wherein the substantially uniform cross section comprises a substantially uniform circular, oval or rectangular cross section.

7. The method of claim 1 , wherein the at least one opening in the stack comprises at least one of a front side opening, a back side trench, or a support pillar opening.

8. The method of claim 7 , wherein forming the at least one opening in the stack comprises forming the at least one front side opening in the stack, and forming at least one layer of the NAND device in the at least one opening comprises forming at least a portion of a memory film and a semiconductor channel in the front side opening.

9. The method of claim 8 , further comprising:

selectively removing portions of the first material layers through the front side opening to form front side recesses between adjacent second material layers;

depositing a blocking dielectric in the at least one front side opening and in the front side recesses, wherein the blocking dielectric comprises a plurality of metal oxide clam shaped regions in the front side recesses;

forming charge storage regions over the blocking dielectric in the front side recesses;

forming a tunnel dielectric over the charge storage regions in the front side opening to form the memory film; and

forming the semiconductor channel material over the tunnel dielectric in the front side opening.

10. The method of claim 9 , further comprising:

forming the back side trench through the stack using a second metal induced localized etch step;

selectively removing the second material layers through the back side trench to form first back side recesses between adjacent first material layers and to expose the first material layers in the back side recesses;

at least partially filling the first back side recesses with an insulating material to form interlayer insulating layers in the respective first back side recesses; and

forming the control gate electrodes between the interlayer insulating layers.

11. The method of claim 10 , wherein:

the first material layers comprise doped silicon layers;

at least partially filling the first back side recesses with an insulating material comprises partially filling the first back side recesses to form interlayer insulating layers that partially fill the respective first back side recesses; and

forming the control gate electrodes between the interlayer insulating layers comprises:

forming a metal layer in the back side trench and in the first back side recesses in contact with sidewalls of the first material layers exposed in the back side trench and in the first back side recesses in contact with back portions of horizontal surfaces of the first material layers exposed in the first back side recesses;

reacting the metal layer with the first material layers to transform back portions of the first material layers into a metal silicide, wherein front portions of the first material layers located between the interlayer insulating layers remain as doped silicon layers to form control gate electrodes having silicide back portions and doped silicon front portions; and

filling remaining portions of the first back side recesses with an insulating material.

12. The method of claim 10 , wherein:

the first material layers comprise doped silicon layers;

at least partially filling the first back side recesses with an insulating material comprises completely filling the first back side recesses to form interlayer insulating layers that completely fill the respective first back side recesses; and

forming the control gate electrodes between the interlayer insulating layers comprises:

selectively recessing the first material layers to form second back side recesses between adjacent interlayer insulating layers; and

filling the second back side recesses with at least one of a metal or metal nitride control gate electrode material through the back side trench to form control gate electrodes having at least one of metal and metal nitride back portions and doped silicon front portions.

13. The method of claim 8 , further comprising:

selectively removing at least portions of the first material layers through the front side opening to form front side recesses between adjacent second material layers;

depositing polysilicon floating gates in the front side recesses;

forming a tunnel dielectric over the floating gates in the front side opening to form a portion of the memory film;

forming the semiconductor channel material over the tunnel dielectric in the front side opening;

forming the back side trench through the stack using a second metal induced localized etch step;

selectively removing the first material layers through the back side trench to form first back side recesses between adjacent second material layers and to expose the floating gates in the back side recesses;

forming a metal or metal nitride layer through the back side trench in the back side recesses in contact with the floating gates;

forming a blocking dielectric through the back side trench in the back side recesses; and

forming control gate electrodes through the back side trench in the back side recesses in contact with the blocking dielectric.

14. The method of claim 13 , wherein the floating gates comprise a polysilicon front portion and a tantalum nitride back portion.

15. The method of claim 13 , further comprising reacting the metal layer with the polysilicon floating gates to form floating gates comprising a metal silicide.

16. The method of claim 1 , further comprising:

forming an etch stop over the substrate prior to forming the stack;

removing the mask layer from the stack;

removing the metal block from a bottom of the at least one opening in the stack, thereby exposing a portion of the etch stop in the at least one opening; and

removing the exposed portion of the etch stop in the at least one opening.

17. The method of claim 3 , further comprising forming barrier layers between adjacent layers of the first material and the second material, the barrier layers comprising an oxide or carbon material that decreases or prevents dopant diffusion between the layers of the first material and the second material.

18. A method of making a monolithic three dimensional NAND device, comprising:

forming a stack of alternating layers of a first polysilicon material and a second material different from the first polysilicon material over a substrate, wherein the first polysilicon material layers comprise doped polysilicon layers;

forming the at least one front side opening in the stack;

forming at least a portion of a memory film and a semiconductor channel in the front side opening;

forming a back side trench through the stack;

selectively removing the second material layers through the back side trench to form first back side recesses between adjacent first polysilicon material layers and to expose the first polysilicon material layers in the back side recesses;

at least partially filling the first back side recesses with an insulating material to form interlayer insulating layers in the respective first back side recesses, wherein at least partially filling the first back side recesses with an insulating material comprises partially filling the first back side recesses to form interlayer insulating layers that partially fill the respective first back side recesses; and

forming control gate electrodes between the interlayer insulating layers, each control gate electrode comprising a front polysilicon portion and a back metal, metal silicide or metal nitride portion which is located farther from the semiconductor channel than the front portion, wherein forming the control gate electrodes between the interlayer insulating layers comprises:

forming a metal layer in the back side trench and in the first back side recesses in contact with sidewalls of the first polysilicon material layers exposed in the back side trench and in the first back side recesses in contact with back portions of horizontal surfaces of the first polysilicon material layers exposed in the first back side recesses;

reacting the metal layer with the first polysilicon material layers to transform back portions of the first polysilicon material layers into a metal silicide, wherein front portions of the first polysilicon material layers located between the interlayer insulating layers remain as doped polysilicon layers to form control gate electrodes having silicide back portions and doped polysilicon front portions; and

filling remaining portions of the first back side recesses with an insulating material.

19. The method of claim 18 , wherein the first polysilicon material layers comprise doped polysilicon layers, the second material layers comprise undoped polysilicon layers, and the front side opening and the back side trench are formed by separate metal induced localized etch steps.