Direct memory access controller
View Patent ↗Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration.
1. A DMA controller comprising:
a channel arbiter configured to select an enabled DMA channel as an active DMA channel for a data transfer and to arbitrate among enabled DMA channels after a beat of data is transferred in the data transfer; and
a channel buffer coupled to the channel arbiter and configured to receive a transfer descriptor of the active DMA channel, the data transfer being performable using the active DMA channel and the transfer descriptor,
wherein the DMA controller is configured to enable a DMA channel by storing a fetched transfer descriptor in a portion of memory.
2. The DMA controller of claim 1 configured to:
determine whether the active DMA channel loses arbitration based on the arbitration among the enable DMA channels after the beat in the data transfer, and
write back the transfer descriptor when the active DMA channel loses arbitration during the data transfer.
3. The DMA controller of claim 1 , wherein the channel arbiter is configured to arbitrate among enabled DMA channels having pending transfer requests after each burst or beat in a given data transfer.
4. The DMA controller of claim 1 , wherein the channel arbiter is configured to receive DMA transfer requests for DMA channels, and
wherein a DMA transfer request of a DMA channel is triggered by one or more of:
a peripheral device,
software, or
an event.
5. The DMA controller of claim 1 configured to communicate with one or more peripheral devices, wherein each peripheral device is associated with a DMA channel.
6. The DMA controller of claim 1 configured to:
perform the data transfer using the active DMA channel and the transfer descriptor of the active DMA channel in the channel buffer, and
update the transfer descriptor of the active DMA channel in the channel buffer.
7. The DMA controller of claim 1 , further comprising:
a first dedicated interface coupled to a first memory portion of a memory module; and
a second dedicated interface coupled to a second memory portion of the memory module, wherein the first memory portion is configured to maintain transfer descriptors of DMA channels, and the second memory portion is configured to maintain transfer descriptors of enabled DMA channels.
8. The DMA controller of claim 1 configured to enable a DMA channel by fetching the transfer descriptor of the DMA channel from a different memory portion of the memory and store the fetched transfer descriptor in the memory portion of the memory.
9. The DMA controller of claim 8 , wherein the channel buffer is configured to receive the transfer descriptor of the DMA channel from the memory portion when the DMA channel is selected as the active DMA channel.
10. The DMA controller of claim 8 , configured to write back a current state of the transfer descriptor of the active DMA channel into the memory portion when the active DMA channel loses arbitration during the data transfer.
11. The DMA controller of claim 1 configured to:
when a number of remaining transfer beats of a transfer descriptor of an enabled DMA channel reaches zero, disable the DMA channel and remove the transfer descriptor of the DMA channel from the memory portion.
12. The DMA controller of claim 1 , further comprising:
a single directional interface for coupling the memory portion to the DMA controller.
13. The DMA controller of claim 1 configured to be coupled to a peripheral bus interface to enable configuration of the DMA controller by an external device.
14. The DMA controller of claim 1 , wherein the transfer descriptor defines a block data transfer and includes one or more parameters: a source address of a transfer, a destination address of the transfer, a number of remaining transfer beats, control data including transfer settings, or an address of a next descriptor, and
wherein the DMA controller is configured to, during the data transfer, update one or more parameters of the transfer descriptor of the active DMA channel including: the source address of a transfer, the destination address of the transfer, or the number of remaining transfer beats.
15. The DMA controller of claim 1 , wherein software is configured to enable or disable DMA channels, and wherein the channel buffer is a register.
16. A method comprising:
selecting an enabled DMA channel as an active DMA channel;
receiving a transfer descriptor of the active DMA channel from a portion of memory, the DMA channel being enabled by storing the transfer descriptor in the memory portion;
performing a data transfer using the active DMA channel and the received transfer descriptor; and
arbitrating among enabled DMA channels after a beat of data is transferred in the data transfer.
17. The method of claim 16 , further comprising:
determining whether the active DMA channel loses arbitration based on the arbitrating among the enabled DMA channels after the beat in the data transfer; and
in response to determining that the active DMA channel loses arbitration, writing back the transfer descriptor of the active DMA channel.
18. The method of claim 17 , wherein determining that the active DMA channel loses arbitration comprises determining that the active DMA channel has a priority that is less than a priority for another enabled DMA channel, and
wherein the method further comprises: in responding to determining that the active DMA channel loses arbitration, interrupting the data transfer and making the another enabled DMA channel the active DMA channel.
19. The method of claim 16 , wherein performing data transfer further includes:
transferring bursts of data;
updating the transfer descriptor of the active DMA channel after each burst of data including a number of remaining transfer beats; and
performing, after each burst of data, one of:
disabling the active DMA channel and clearing the transfer descriptor of the active DMA channel when the number of remaining transfer beats reaches zero, or interrupting the data transfer and re-storing the updated transfer descriptor of the active DMA channel when losing arbitration.
20. The method claim 16 , wherein the transfer descriptor includes one or more parameters: a source address of a transfer, a destination address of the transfer, the number of remaining transfer beats, control data including transfer settings, or an address of a next descriptor, and
wherein the method further comprises updating one or more parameters of the transfer descriptor including: the number of remaining transfer beats, the source address of a transfer, or the destination address of the transfer.
21. The method of claim 16 , further comprising: enabling two or more direct memory access (DMA) channels by:
fetching transfer descriptors of the DMA channels from a different portion of the memory; and
storing the received transfer descriptors of the enabled DMA channels in the memory portion.
22. The method of claim 16 , further comprising:
retrieving a second transfer descriptor of the active DMA channel when a number of remaining transfer beats of the transfer descriptor reaches zero, wherein the second transfer descriptor is retrieved using an address of a next descriptor of the transfer descriptor.
23. The method of claim 16 , further comprising:
assigning priority levels to each DMA channel, wherein a DMA channel with higher priority level interrupts any ongoing data transfers through DMA channels with lower priority levels.
24. A DMA controller comprising:
two or more DMA channels;
a channel arbiter configured to select an enabled DMA channel as an active DMA channel for a data transfer based on one or more criteria including arbitrating after a beat of data is transferred in the data transfer; and
a channel buffer configured to receive a transfer descriptor of the active DMA channel from memory for the data transfer, wherein the DMA controller is configured to enable the DMA channel by storing the transfer descriptor in the memory,
wherein the DMA controller is configured to determine whether the active DMA channel loses arbitration based on the arbitration after the beat in the data transfer and write back the transfer descriptor of the active DMA channel into the memory when the active DMA channel loses arbitration during the data transfer.