System, method and apparatus to relieve stresses in a semiconductor die caused by uneven internal metallization layers

1. A semiconductor die comprising:

a plurality of semiconductor devices formed in a portion of a semiconductor wafer;

an electrical interconnect structure formed over the plurality of semiconductor devices and providing electrical connections to the plurality of semiconductor devices, the electrical interconnect structure defined from a plurality of metallization layers, each of the metallization layers including conductive lines, wherein at least one portion of at least one of the plurality of metallization layers includes a density of the conductive lines that varies as compared to the other portions of the metallization layers; and

at least one support structure formed in the electrical interconnect structure to provide lateral support to substantially prevent at least one of a curving stress or a bending stress in the portion of the semiconductor wafer;

wherein the at least one support structure is formed in at least two layers of the electrical interconnect structure and at least one anchor structure is formed through any intervening layers between the at least two layers to connect the portions of the at least one support structure in each of the at least two layers.

2. The semiconductor die of claim 1 , wherein the portion of the semiconductor wafer is a thinned semiconductor wafer having a thickness of between about 40 um and about 200 um.

3. The semiconductor die of claim 2 , wherein the thinned semiconductor wafer is thinned after the plurality of semiconductor devices are formed in the portion of the semiconductor wafer.

4. The semiconductor die of claim 1 , wherein the at least one support structure is formed in a single layer of the electrical interconnect structure.

5. The semiconductor die of claim 1 , wherein the at least one support structure has different respective widths in each of the at least two layers.

6. The semiconductor die of claim 1 , wherein the at least one support structure is formed in a metal used to form a plurality of electrical interconnects in the electrical interconnect structure.

7. The semiconductor die of claim 1 , wherein the at least one support structure is formed of a conductive metal used to form a plurality of electrical interconnects in the electrical interconnect structure and wherein the least one support structure is not a portion of one of the plurality of electrical interconnects.

8. The semiconductor die of claim 1 , wherein the at least one support structure is formed of a conductive metal used to form a plurality of electrical interconnects in the electrical interconnect structure and wherein the least one support structure forms a portion of one of the plurality of electrical interconnects.

9. The semiconductor die of claim 1 , wherein the at least one support structure is formed of a conductive metal used to form a plurality of electrical interconnects in the electrical interconnect structure and wherein the least one support structure forms at least a portion of an electrical device in the electrical interconnect structure.

10. The semiconductor die of claim 1 , wherein the at least one support structure is a portion of a wafer support structure, wherein the wafer support structure extends across more than one semiconductor die.

11. The semiconductor die of claim 1 , wherein the semiconductor die is one of a plurality of stacked semiconductor dies in a predefined form factor package, the form factor package including a plurality of connect structures coupling the plurality of stacked semiconductor dies to a contact pad structure.

12. The semiconductor die of claim 1 , wherein the plurality of semiconductor devices include memory cells.

13. The semiconductor die of claim 1 , wherein the plurality of semiconductor devices include 3D memory cells.

14. The semiconductor die of claim 1 , wherein the plurality of semiconductor devices form a processor.

15. A semiconductor die comprising:

a plurality of semiconductor devices formed in a portion of a semiconductor wafer;

an electrical interconnect structure formed over the plurality of semiconductor devices and providing electrical connections to the plurality of semiconductor devices, the electrical interconnect structure defined from a plurality of metallization layers, each of the metallization layers including conductive lines, wherein at least one portion of at least one of the plurality of metallization layers includes a density of the conductive lines that varies as compared to the other portions of the metallization layers;

a first support structure formed in a first one of the metallization layers, the first support structure having a first width;

a second support structure formed in a second one of the metallization layers, the second support structure having a second width different than the first width; and

an anchor structure formed through any layers intervening between the first metallization layer and the second metallization layer, wherein the first support structure, the second support structure and the anchor structure provide lateral support to substantially prevent at least one of a curving stress or a bending stress in the portion of the semiconductor wafer.

16. The semiconductor die of claim 15 , wherein the at least one support structure is formed of a conductive metal used to form a plurality of electrical interconnects in the electrical interconnect structure and wherein the least one support structure is not a portion of one of the plurality of electrical interconnects.

17. The semiconductor die of claim 15 , wherein the at least one support structure is formed of a conductive metal used to form a plurality of electrical interconnects in the electrical interconnect structure and wherein the least one support structure forms a portion of one of the plurality of electrical interconnects.

18. The semiconductor die of claim 15 , wherein the first support structure has a first length corresponding to a length of the semiconductor die.